Hi Ahmad,
If you are interested in MATLAB code (in order to simulate the fixed-point
numerics and pick good CIC filter parameters before writing the HDL code),
you may want to evaluate the CIC filtering capabilities in the MATLAB Filter
Design Toolbox.
<http://www.mathworks.com/access/helpdesk/help/toolbox/filterdesign/mfilt.ci
cdecim.shtml>
Cheers,
Steve
"Ahmad" <eng_ak@link.net> wrote in message
news:3014031e.0308272345.4bc3473f@posting.google.com...

> Yes, but I will be building it on ASIC (A/D), so it's not on an FPGA
> :( Still any matlab or vhdl code are highly appreciated. I will of
> course take a look on their docs as well.
>
> Thnx
>
> "Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message

> > "Ahmad" <eng_ak@link.net> wrote in message
> > news:3014031e.0308271127.2115fd42@posting.google.com...
> > > Hi all,
> > >
> > > I am currently in the process of designing a decimation filter for a
> > > 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a
> > > FIR filter.
> > >
> > > I am facing great difficulty understanding such filter, as my
> > > experience in usually with analog circuits, and not DSP.
> > >
> > > My question basically, is there any free Matlab or VHDL code to get me
> > > started simulating either the whole decimation filter, or only the CIC
> > > filter. I would value any suggestion very much. I've been reading
> > > papers for more than a month now, and all of them concentrate on the
> > > mathematical part without mentioning the implementation part.
> > >
> > > Any VHDL code would be greatly valued.
> >
> > I'm not an FPGA designer - so I don't have VHDL to help you out, but

both

> > Altera and Xilinx have cores that do this for you already. These are
> > parameterized, which means you can plug their cores into your design and
> > select the appropriate bit widths, etc. Given that your background is in
> > analog design, I highly recommend this route.
> > Both companies also have extensive data sheets for these core that

explain

> > the guts of their cores to a reasonable extent. I *think* they also have
> > examples on how to figure out the filter params based on certain
> > requirements.
> >
> > Cheers
> > Bhaskar
> >
> > >
> > > Also, another question. Is there any formula for determining the
> > > required stop band attenuation for the decimation filter based on
> > > specs from the sigma-delta modulator??
> > >
> > > Thanks

Reply by Ahmad●August 28, 20032003-08-28

Yes, but I will be building it on ASIC (A/D), so it's not on an FPGA
:( Still any matlab or vhdl code are highly appreciated. I will of
course take a look on their docs as well.
Thnx
"Bhaskar Thiagarajan" <bhaskart@deja.com> wrote in message news:<bijb1o$9v4um$1@ID-82263.news.uni-berlin.de>...

> "Ahmad" <eng_ak@link.net> wrote in message
> news:3014031e.0308271127.2115fd42@posting.google.com...
> > Hi all,
> >
> > I am currently in the process of designing a decimation filter for a
> > 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a
> > FIR filter.
> >
> > I am facing great difficulty understanding such filter, as my
> > experience in usually with analog circuits, and not DSP.
> >
> > My question basically, is there any free Matlab or VHDL code to get me
> > started simulating either the whole decimation filter, or only the CIC
> > filter. I would value any suggestion very much. I've been reading
> > papers for more than a month now, and all of them concentrate on the
> > mathematical part without mentioning the implementation part.
> >
> > Any VHDL code would be greatly valued.
>
> I'm not an FPGA designer - so I don't have VHDL to help you out, but both
> Altera and Xilinx have cores that do this for you already. These are
> parameterized, which means you can plug their cores into your design and
> select the appropriate bit widths, etc. Given that your background is in
> analog design, I highly recommend this route.
> Both companies also have extensive data sheets for these core that explain
> the guts of their cores to a reasonable extent. I *think* they also have
> examples on how to figure out the filter params based on certain
> requirements.
>
> Cheers
> Bhaskar
>
> >
> > Also, another question. Is there any formula for determining the
> > required stop band attenuation for the decimation filter based on
> > specs from the sigma-delta modulator??
> >
> > Thanks

Reply by Ray Andraka●August 27, 20032003-08-27

The analysis, as well as modelling is made a lot easier if you recognize
that the CIC is just a recursive expression of the boxcar filter. An N
tap CIC with a decimation ratio of R is equivalent to an N*R tap boxcar
filter with the output sampled every R samples. The boxcar filter is
simply the sum of the last N inputs.
Ahmad wrote:

> Hi all,
>
> I am currently in the process of designing a decimation filter for a
> 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a
> FIR filter.
>
> I am facing great difficulty understanding such filter, as my
> experience in usually with analog circuits, and not DSP.
>
> My question basically, is there any free Matlab or VHDL code to get me
> started simulating either the whole decimation filter, or only the CIC
> filter. I would value any suggestion very much. I've been reading
> papers for more than a month now, and all of them concentrate on the
> mathematical part without mentioning the implementation part.
>
> Any VHDL code would be greatly valued.
>
> Also, another question. Is there any formula for determining the
> required stop band attenuation for the decimation filter based on
> specs from the sigma-delta modulator??
>
> Thanks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

Reply by Bhaskar Thiagarajan●August 27, 20032003-08-27

"Ahmad" <eng_ak@link.net> wrote in message
news:3014031e.0308271127.2115fd42@posting.google.com...

> Hi all,
>
> I am currently in the process of designing a decimation filter for a
> 16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a
> FIR filter.
>
> I am facing great difficulty understanding such filter, as my
> experience in usually with analog circuits, and not DSP.
>
> My question basically, is there any free Matlab or VHDL code to get me
> started simulating either the whole decimation filter, or only the CIC
> filter. I would value any suggestion very much. I've been reading
> papers for more than a month now, and all of them concentrate on the
> mathematical part without mentioning the implementation part.
>
> Any VHDL code would be greatly valued.

I'm not an FPGA designer - so I don't have VHDL to help you out, but both
Altera and Xilinx have cores that do this for you already. These are
parameterized, which means you can plug their cores into your design and
select the appropriate bit widths, etc. Given that your background is in
analog design, I highly recommend this route.
Both companies also have extensive data sheets for these core that explain
the guts of their cores to a reasonable extent. I *think* they also have
examples on how to figure out the filter params based on certain
requirements.
Cheers
Bhaskar

>
> Also, another question. Is there any formula for determining the
> required stop band attenuation for the decimation filter based on
> specs from the sigma-delta modulator??
>
> Thanks

Reply by Ahmad●August 27, 20032003-08-27

Hi all,
I am currently in the process of designing a decimation filter for a
16bit Sigma Delta ADC. I suspect it will be a CIC filter followed by a
FIR filter.
I am facing great difficulty understanding such filter, as my
experience in usually with analog circuits, and not DSP.
My question basically, is there any free Matlab or VHDL code to get me
started simulating either the whole decimation filter, or only the CIC
filter. I would value any suggestion very much. I've been reading
papers for more than a month now, and all of them concentrate on the
mathematical part without mentioning the implementation part.
Any VHDL code would be greatly valued.
Also, another question. Is there any formula for determining the
required stop band attenuation for the decimation filter based on
specs from the sigma-delta modulator??
Thanks