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Hi, Kismat Singh, To configure the EDMA for any channel (or QDMA request) to interrupt the CPU: 1. Set CIEn to '1' in the CIER 2. Set TCINT to '1' in channel options 3. Set Transfer Complete Code to n in channel options And when you want to clear CIPR bits you should writing a '1' to the relevant bits, writing a 0 has no effect. Tao Wang ShangHai, China ----- Original Message ----- From: "kismat singh" <> Date: Fri, 04 Jul 2003 19:26:58 +0530 To: Subject: [c6x] EDMA interrupt problem : URGENT Re: Hi All, Re: I am working on TEB6416. I am facing a very wierd problem in the EDMA interrupt. After completion of very first DMA the CPU services the EDMA ISR. In the ISR, I make the corresponding bit in CIPR register as 0. For all subsequent EDMA transfer completes, CPU doesn't goes to the ISR. I have enabled interuppt for other EDMA transfers also and I have given Interuppt threshold as 6. The subsequent EDMA transfers are proper though. Re: Re: Thanks in advance for any help. Re: Re: Regards Re: Kismat Re: Re: Re: Re: _____________________________________ Re: Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. Re: Re: _____________________________________ Re: About this discussion group: Re: Re: To Join: Send an email to Re: Re: To Post: Send an email to Re: Re: To Leave: Send an email to Re: Re: Archives: http://www.yahoogroups.com/group/c6x Re: Re: Other Groups: http://www.dsprelated.com Re: Re: Re: ">http://docs.yahoo.com/info/terms/ Re: Re: -- __________________________________________________________ Sign-up for your own FREE Personalized E-mail at Mail.com http://www.mail.com/?sr=signup CareerBuilder.com has over 400,000 jobs. Be smarter about your job search http://corp.mail.com/careers |