>On Tue, 02 Apr 2013 01:04:28 -0500, Mimar wrote:
>
>>>On Thu, 28 Mar 2013 06:32:52 -0500, Mimar wrote:
>>>
>>>>>On Wed, 27 Mar 2013 17:40:08 -0500, Mimar wrote:
>>>>>
>>>>>>>On Wed, 27 Mar 2013 09:53:41 -0500, Mimar wrote:
>>>>>>>
>>>>>>>> Hello,
>>>>>>>>
>>>>>>>> can somebody give me an advice? I have decided to use SRF-PLL
>> system
>>>>>> for
>>>>>>>> frequency tracking/estimation in 3 phase power grid recently but
>>>> there
>>>>>>>> is some problems:
>>>>>>>> 1. long settling time, but I beliave, I will solve this soon 2.
if
>> I
>>>>>>>> am trying to change frequency constantly(= frequency ramp), the
>>>>>>>> estimation frequency curve is above reference curve and the
>>>>>>>> distanc
>>>> of
>>>>>>>> these
>>>>>> curves
>>>>>>>> gets bigger with time. So I can say, resulting frequency does not
>>>>>> follow
>>>>>>>> grid frequency by frequency ramp.
>>>>>>>>
>>>>>>>> In other situation it works quite well. I have been testing a lot
>> of
>>>>>> PLL
>>>>>>>> systems in Matlab for long time, but problem with frequency ramp
>>>>>>>> continues.
>>>>>>>>
>>>>>>>> Thank you for your ideas.
>>>>>>>>
>>>>>>>> PS: I am sorry, my English is not good.
>>>>>>>
>>>>>>>First, I question whether a PLL is really the best approach for
this
>>>>>>>sort
>>>>>>
>>>>>>>of thing. Given that this is a DSP group, I'm assuming that you're
>>>>>>>doing
>>>>>>
>>>>>>>this digitally. Assuming that you have the processing power
>>>>>>>available,
>>>>>>>there are better ways to estimate frequency than by implementing a
>>>>>>>traditional PLL.
>>>>>>>
>>>>>>>Ultimately, a phase locked loop is an excellent solution to the
>>>>>>>problem when your signal processing capabilities are largely
limited
>>>>>>>to analog circuits. When you can do DSP, there are better ways.
>>>>>>>
>>>>>>>I would consider an approach that samples your signal over some
>>>>>>>fixed interval, then does a best-fit of a sine wave to that signal.
>>>>>>>The frequency of the sine wave that fits best is then your
frequency
>>>>>> estimate.
>>>>>>>
>>>>>>>Second, if you still feel that you absolutely, positively, must
>>>>>>>stick with a PLL, please share some details. If you are
>>>>>>>implementing the PLL correctly and in the canonical way, then your
>>>>>>>problem with
>> ramping
>>>>>>>is
>>>> in
>>>>>>>your loop filter. But over the years I've seen PLL circuits and
>>>>>>>algorithms messed up in some pretty astounding ways, and even seen
a
>>>> few
>>>>>>>very non-canonical arrangements that worked quite well indeed. So
I
>>>>>>>can't just issue general directives without seeing what you're
>>>>>>>doing.
>>>>>>>
>>>>>>>PLEASE DON'T BOTHER WITH POSTING JUST CODE!!
>>>>>>>
>>>>>>>Post a block diagram, or at least a three- or four-line algorithmic
>>>>>>>description. If you must, post the code with it, but post a block
>>>>>>>diagram. If all you have is code, and you can't draw up a block
>>>> diagram
>>>>>>>or extract the essentials of the algorithm from it, then chances
are
>>>>>>>that
>>>>>>
>>>>>>>you don't really know what it is that you are doing. In that
event,
>>>>>>>as you build your block diagram you may find your problem without
>>>>>>>having
>>>> to
>>>>>>>ask us further.
>>>>>>>
>>>>>>>--
>>>>>>>My liberal friends think I'm a conservative kook. My conservative
>>>>>>>friends think I'm a liberal kook. Why am I not happy that they have
>>>>>>>found common ground?
>>>>>>>
>>>>>>>Tim Wescott, Communications, Control, Circuits & Software
>>>>>>>http://www.wescottdesign.com
>>>>>>>
>>>>>>>
>>>>>> Hello Tim,
>>>>>>
>>>>>> the PLL I am testing now, is DDSRF-PLL
>>>>>> (http://www.icrepq.com/icrepq%2712/826-luna.pdf). I think, it is a
>>>>>> suitable structure for purpose, I will use it to. As you correctly
>>>>>> mentioned, PLL is implemented in DSP (FreeScale 56800E family)
using
>>>>>> simple algorithm: in first stage there is provided Clark transform,
>>>>>> then twice DQ transform and at the end some IIR filters and PI
>>>>>> controller with anti-wind-up. Sample frequency of input signals (=
3
>>>>>> phase voltage) I chosed, is 5 kHz. I have tested as pure signal (50
>>>>>> Hz sinus) and signals with harmonic pollution.
>>>>>> The rate of frequency change is different. I have tested 0.02
Hz/0.2
>>>>>> s,
>>>>>> 0.5 Hz/0.2 s ......and the result is the same - output curve of
>>>>>> estimated frequency cannot follow input frequency. I tried adjust
Ki
>>>>>> and Kp constant in PI controller for million times to improve it,
>>>>>> but without good result.
>>>>>>
>>>>>> I think, the solution of this problem will be in transition
>>>>>> response. PLL doesn´t enough time to stabilize itself.
>>>>>
>>>>>You have two potential problems. I'm not sure which one applies to
>> your
>>>>>situation.
>>>>>
>>>>>The first is just the PLL bandwidth. As the frequency starts and
>>>>>stops ramping, the loop will take time to react.
>>>>>
>>>>>The second is the fact that you've got a type 2 loop (meaning the
>>>>>open- loop path has two pure integrators). A type 2 loop simply
>>>>>cannot track a
>>>>
>>>>>ramp with zero error -- you can increase the loop gain (and hence the
>>>>>bandwidth), but you do so at the expense of increasing the bandwidth
>>>>>(and
>>>>
>>>>>hence the noise sensitivity) and possibly decreasing the loop
>> stability.
>>>>>
>>>>>You can use a proportional-double integrator loop (i.e., use a loop
>>>>>whose
>>>>
>>>>>transfer function is kp + ki1 /(z-1) + ki2/(z-1)^2). That will track
>>>>>a steady ramp with zero error, but keeping all else equal it will
have
>>>>>worse transient behavior to frequency steps and at the onset and
>> endings
>>>>>of frequency ramps.
>>>>>
>>>>>I still question the whole PLL approach. There _are_ times when PLLs
>> in
>>>>>software make sense -- but there are times when implementing one
>> instead
>>>>>of using some more modern phase/frequency detection scheme is like
>>>>>sitting on the floor of a modern shop and using stone tools to do
some
>>>>>task.
>>>>>
>>>>>--
>>>>>Tim Wescott Control system and signal processing consulting
>>>>>www.wescottdesign.com
>>>>>
>>>>>
>>>> Before several minutes I tried to change PI loop to
>>>> proportional-double integrator loop as you mentioned above. But I am
>>>> not sure my difference equation of transfer function is correct:
>>>> kp + ki/(z-1) I wrote as: y(n) = (kp + ki)*e(n) + y(n-1); and
>>>> ki2/(z-1)^2 I wrote as: y(n) = ki2*e(n) + (2*y(n-1) - y(n-2));
>>>>
>>>> where e ... input error
>>>> y ... output from loop
>>>>
>>>> Can you control it, please?
>>>
>>>I do this sort of thing by breaking out the integrator states
>>>separately. This minimizes your chances of having problems with
>>>numerical precision, makes the coding more transparent, and makes it
>>>easier to apply anti-windup to the integrators.
>>>
>>>x1(n) = x1(n-1) + ki1 * e(n)
>>>(limit x1(n) as necessary)
>>>
>>>x2(n) = x2(n-1) + ki2/ki1 * x1(n)
>>>(limit x2(n) as necessary)
>>>
>>>y(n) = kp * e(n) + x1 + x2
>>>
>>>Of the forms that really make the integrators explicit, the practice of
>>>putting the integrator gain at the input of the integrators means two
>>>things: one, you won't get jumps in the output if you tune on-line, and
>>>two, the "meaning" of your integrator limits more or less stay the
same.
>>>
>>>I'm assuming that you're tuning this in the frequency domain using Bode
>>>plots or Nyquist plots -- yes? If you're not ready to step up to that,
>>>I
>>
>>>probably should not have recommended a double-integrator controller.
>>>
>>>Note, too, that PLLs that use a double-integrating loop filter are
often
>>>designed such that the second integrator (x2, ki2) remains off with x2
=
>>>0 until the PLL has achieved lock -- if you don't do that, then your
PLL
>>>frequency can go off into the weeds and you'll never actually lock.
>>>
>>>--
>>>Tim Wescott
>>>Control system and signal processing consulting www.wescottdesign.com
>>>
>>>
>> I have tested the double-integrating loop filter mentioned above this
>> weekend, but the result is the same. Problem still continues. If you
can
>> see curves of input and output frequency, you can visit this link:
>> http://uloz.to/xpTLixf/pllfrekvence-jpg. Red is reference frequency and
>> blue is the output of system.
>> At the moment I am studying some documents about PID etc., so I believe
>> I will have a brainwave soon :-).
>
>I don't get a picture on that site. If there's a button I need to press,
>alas, I don't read the language.
>
>I'll reiterate what I think is causing you trouble: if you're trying to
>track a steady ramp, then the two-integrator loop will work splendidly.
>If you're trying to track a ramp that starts and stops, then the two-
>integrator loop will take some time to settle out to the correct answer,
>and may actually be worse than a one-integrator solution.
>
>If you use a more "modern DSP-ish" batch approach that starts by assuming
>that you're estimating the frequency of a sine wave that has both an
>offset and a ramp, then for any segment that you analyze that has a
>steady ramp, you'll be as close to correct as noise will allow.
>
>I'd suggest that you take your sample, split it into cycles at the
>nominal frequency (50Hz?), extract a phase estimate for each defined
>cycle, "unwind" the phase estimate (i.e., make sure that -pi and pi
>connect instead of making a sawtooth), then find the offset and slope of
>the whole thing. For moderate to low noise, and small frequency
>variations from nominal, this should be very close to optimum. And you
>won't have to mess around with phase-locked loops.
>
>--
>My liberal friends think I'm a conservative kook.
>My conservative friends think I'm a liberal kook.
>Why am I not happy that they have found common ground?
>
>Tim Wescott, Communications, Control, Circuits & Software
>http://www.wescottdesign.com
>
I think it will be better, I'll give here my code of proposed PLL written
in Matlab:
%..........................................................................
%
% Test of SFR-PLL
%
%..........................................................................
clc;
clear all;
close all;
%..........................................................................
f = 40;
fvz = 5000;
Ts = 1/fvz;
%..........................................................................
faze = 0;
reg_P = 0;
delka_sig = 3000;
%% test signal generation
SNR = 60; % noise to signal ratio
AMP1 = 10;
NSAMP = AMP1/(10^(SNR/20)) % amplitude for SNR
for n = 0 : 1 : delka_sig-1 % delka_sig is length of signal in English
%% variable frequencies
if n < 370
f = 50;
elseif n >= 370 & n < 1200
if mod(n, 200)
f = f + 0.01;
else
f = f;
end
elseif n >= 1200 & n < 1500
f = 57;
else
if mod(n, 100)
f = f - 0.01;
else
f = f;
end
end
reference_f(n+1) = f; % vector of freq.
% harmonics
uA(n+1) = AMP1 * sin(2*pi*f*Ts*n); % 1.
uB(n+1) = AMP1 * sin(2*pi*f*Ts*n + (2*pi)/3);
uC(n+1) = AMP1 * sin(2*pi*f*Ts*n - (2*pi)/3);
uA3(n+1) = 1 * sin(3*2*pi*f*Ts*n); % 3.
uB3(n+1) = 1 * sin(3*2*pi*f*Ts*n + (2*pi)/3);
uC3(n+1) = 1 * sin(3*2*pi*f*Ts*n - (2*pi)/3);
uA5(n+1) = 0.8 * sin(5*2*pi*f*Ts*n); % 5.
uB5(n+1) = 0.8 * sin(5*2*pi*f*Ts*n + (2*pi)/3);
uC5(n+1) = 0.8 * sin(5*2*pi*f*Ts*n - (2*pi)/3);
uA7(n+1) = 0.4 * sin(7*2*pi*f*Ts*n); % 7.
uB7(n+1) = 0.4 * sin(7*2*pi*f*Ts*n + (2*pi)/3);
uC7(n+1) = 0.4 * sin(7*2*pi*f*Ts*n - (2*pi)/3);
end
noise = NSAMP * randn(size(delka_sig)); % noise inserting
%% now only pure signal
uA = uA; % + uA3 + uA5 + uA7 + noise;
uB = uB; % + uB3 + uB5 + uB7 + noise;
uC = uC; %+ uC3 + uC5 + uC7 + noise;
%........data
preparing....................................................
uD = zeros(1, delka_sig);
uQ = zeros(1, delka_sig);
f_out = zeros(1, delka_sig); % output (estimated) frequency
reg_I = zeros(1, delka_sig); % integer part of controller
reg_ID = zeros(1, delka_sig); % second integer part of controller
w_out = zeros(1, delka_sig); % output angular frequency
phase = zeros(1, delka_sig); % output phase
contr = zeros(1, delka_sig); % other PI controller
error = zeros(1, delka_sig); % input error for controller
%..........................................................................
%........parameters........................................................
%% constant for controller
Kp = 250; %
Ki = 50;
Ki_1 = 0.001;
Ki_2 = -0.5;
a1 = ((Kp*Ts)/(2*Ki)) - Kp;
a2 = ((Kp*Ts)/(2*Ki)) + Kp;
b1 = 0.5;
%% MAIN LOOP
for n = 3 : 1 : delka_sig
%% Clark transformation
Ualpha = (2*uA(n) - uB(n) - uC(n))/3; % slozka ALFA
Ubeta = (uB(n) - uC(n))/1.73205; % slozka BETA
%% Park transformation
uD(n) = Ualpha*cos(phase(n-1)) + Ubeta*sin(phase(n-1));
uQ(n) = Ubeta *cos(phase(n-1)) - Ualpha*sin(phase(n-1));
% error
error(n) = uQ(n);
%% PI controllers
%{
% P
reg_P = Kp * error(n);
% I
% first integrator
reg_I(n) = reg_I(n-1) + Kp * 1/Ki_1 * Ts * (error(n) + error(n-1))/2;
% second integrator
reg_ID(n) = reg_ID(n-1) + Ki_2/Ki_1 *reg_I(n)*Ts;
%}
% alternative for PI
regul(n) = a1*error(n) + a2*error(n-1) + b1*regul(n-1); % it is better
than above
% angular frequency
w_out(n) = 314.159 + regul(n); % + reg_I(n); %+ reg_ID(n);
% phase
phase(n) = phase(n-1) + w_out(n) * Ts;
if phase(n) > 2*pi
phase(n) = 0;
elseif phase(n) < 0
phase(n) = 2*pi;
else
phase(n) = phase(n);
end
% output, estimated frequency
f_out(n-1) = w_out(n)/(2*pi);
end
%........graphic output...................................................
osax = [0 : 1 : delka_sig-1]*Ts; % x axis
figure(1)
subplot(2,1,1)
hold on
plot(uA(1:500), 'r');
plot(uB(1:500), 'c');
plot(uC(1:500), 'g');
hold off
subplot(2,1,2)
hold on
plot(osax, reference_f, 'r', 'LineWidth', 2);
plot(osax, f_out, 'c', 'LineWidth', 1.5);
legend('In', 'Out');
grid on
figure(2)
subplot(2,1,1)
hold on
plot(uA(1:500), 'r');
plot(uQ(1:500), 'c');
grid on
subplot(2,1,2)
plot(phase(1:500), 'c');
grid on