I found this, in familiy manual, page 7-6. After executing the JSR instruction and stacking the PC and SR, the core raises the IPL bit to 1 to disallow any level 0 interrupts. Therefore, make sure that your interrupt service routine exits with an RTI instruction (use a #pragma interrupt saveall or add a asm(rti) at the end of your ISR. Other than this, I don't know what else could be masking your interrupts... MPF ----- Original Message ----- From: "max_mont" <> To: <> Sent: Thursday, January 15, 2004 4:37 PM Subject: [motoroladsp] IRQA problem Hi, On my board with 56F807, a signal at 2 Hz comes on IRQA pin which must provocate an ISR every 500 ms. When I debug, the program goes in ISRA only one time and the others ISR are disable (SCI, timer, ...) I don't know what is the problem. I set IRQA on rising edge and then I enable it. Have you got an idea. Many thanks in advance for your help. Maxime. _____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: To Post: To Leave: Archives: http://www.yahoogroups.com/group/motoroladsp More Groups: http://www.dsprelated.com/groups.php3 |