Barry,
Something just struck me about your problem...
It worked with a polling loop, correct??
I remember a problem that I had with the 6211 - when the CPU does only word
accesses, the byte enables are not required. However, for some reason,
when you access the same memory with EDMA, you must have the byte enables
connected for correct operation. Check your schematics to see if the byte
enables are not hooked up.
mikedunn
Mike Dunn <m...@sbcglobal.net>
wrote:
Barry,
I am not familiar with the AIC23 EVM h/w, but it sounds like you may be
doing 16 bit writes while the h/w only supports word writes...
mikedunn
bg_ie <b...@yahoo.com> wrote:
Hi,
I'm writing a driver to stream audio between a
C6711DSK and an AIC23EVM Codec daughter board. In order to simply the
writing of this code, I first of all implemented this driver for polling
mode, that is, I poll the values in RRDY and XRDY in the SPCR of the
McBSP0 register. Now I'm attempting to implement this in EDMA
mode.
The AIC23 operates in Mastermode, generating both CLK and Frame
Syncs. Frames are 32 bits long, 16 bits for the left channel, 16 bits for the right. A 16 bit value of 0x8001 represents -1, 0x7fff represents
+1, and 0x0000 represents 0. 0.1 is represented by 0x0ccc, and -0.1 is
equal to 0xf334.
The problem I'm having is that I only get the
expected output from the Codec if I output the same signal to each
channels. So lets say I wish to output a square wave, for simplicity I
send -
f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, 0ccc0ccc,
0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc,
0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc,
0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc,
0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc,
0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc, 0ccc0ccc,
and so
on... where commas separate each of the 32 bit samples (left and right) I
pass on to the EDMA.
So the first outputted value is f334f334 - thats
f334 for both left and right channels. This gives a me a square wave for
both channels. But
if I attempt to output the following I dont get what would have expected -
0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334,
0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334,
0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334,
0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334,
0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334, 0cccf334,
0cccf334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334, f334f334, f334f334, f334f334, f334f334, f334f334, f334f334,
f334f334,
I should be getting the same square wave as before in one
channel, and a DC of -0.1 in the other. Instead, I get -0.1 for both
channels when f334f334 is being
outputted (as expected), but when 0cccf334 is outputted, instead of
getting -0.1 and 0.1 in either channel, I get an oscillation ranging from
between 0.1 and around 0.03 Volts in both channels. So pictorially this is
what I'm getting in both channels (despite the fact that both
channels should be different) -
* * * * * * * * * ** * * ** ** *
* ** ** * * ** * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * ********* ********* *********
If I output -
0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334,
0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334,
0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334,
0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334,
0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334, 0000f334,
0000f334, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc,
00000ccc, 00000ccc, 00000ccc, 00000ccc,
00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc,
00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc,
00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc, 00000ccc,
00000ccc, 00000ccc, 00000ccc, 00000ccc,
Then I get something like -
* * * * * * * * * ** * * ** ** * * ** ** * * ** * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * ** * * **
** * * ** ** * * * * * * * * * * * * *
I thought that maybe this
problem was related to the external frame sync problem, but perhaps its
not,
Any ideas as to what might be wrong?
This is how I
configure the EDMA -
/* Config Structures */ EDMA_Config
DSS_edmaMcbspRx = { 0x287D0000, /* Option */ 0x30000000, /* Source
Address - Numeric */ 0x00000000, /* Transfer Counter - Numeric */ 0x00000000, /* Destination Address - Numeric */ 0x00000002, /* Index
register - Numeric */ 0x00000000 /* Element
Count Reload and Link Address */ };
EDMA_Config DSS_edmaMcbspTx
= { 0x4B1C0000, /* Option */ 0x00000000, /* Source Address - Numeric
*/ 0x00000000, /* Transfer Counter - Numeric */ 0x30000000, /*
Destination Address - Numeric */ 0x00000002, /* Index register - Numeric
*/ 0x00000000 /* Element Count Reload and Link Address */ };
Interrupt Mode is set up for RRDY and XRDY.
Thanks for your
help,
Barry.
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