I am currently working on the C54CST version of the DSP and am having
issues with configuring a DMA channel.

What I am trying to do is capture(recieve) the DATA coming in on MCBSP
0 and  just simply store the data in memory to read it later
(basically I am testing part of the functionality of the DMA). MCBSP 0
is connected to an ST-BUS device (TP3071 CODEC) and the clock and
frame sync are both from external sources. Originally I checked to
make sure if my MCBSP configuration is correct by seeing if the REVT0
(recieve interrupt 0) was firing due to the data being sent by the
codec. In my ISR for the MCBSP0, I simply blinked the lights on the
EVM board and it was succesfull. 

Now when I use DMA Channel 2 and tie the interrupt to REVT0 of MCBSP 0
the DSP never jumps into the ISR of the DMA channel. I am assuming its
not recieveing a SYNC event.

If anyone can help me with this I would be forever grateful.

Also below I have posted my MCBSP and DMA channel config.
*Note I did not add the lines of code where I enable the MCBSP and DMA
channel. Also the part where I enable the INT0SEL bit where I mask the
ineterrupts for channel 2 and 3 (added below).

/* Enable mask of DMA channel 2 and 3 interrupts by setting 
 * the interrupt selector value in DMA priority and enable  
 * register, DMPREC                                         
 */
  DMA_FSET(DMPREC,INTOSEL,DMA_DMPREC_INTOSEL_CH2_CH3);

Haider Ali Baig
Design Engineer
Future Technologies Pvt. Lmtd.
+11 97 321 223 2991 
haideralibaig@haid...

/* CODE */
void DMACH2_init(void){

DMA_Config dmaConfigCH2 = {
1,                  	        /* Set Priority */
DMA_DMMCR_RMK(
DMA_DMMCR_AUTOINIT_ON,
DMA_DMMCR_DINM_ON,
DMA_DMMCR_IMOD_FRAME_AND_BLOCK,
DMA_DMMCR_CTMOD_MULTIFRAME,
DMA_DMMCR_SLAXS_OFF,
DMA_DMMCR_SIND_NOMOD,
DMA_DMMCR_DMS_DATA,
DMA_DMMCR_DLAXS_OFF,
DMA_DMMCR_DIND_DMIDX0,
DMA_DMMCR_DMD_DATA
),/* DMMCR */

DMA_DMSFC_RMK(
DMA_DMSFC_DSYN_REVT0,
DMA_DMSFC_DBLW_OFF,
DMA_DMSFC_FRAMECNT_OF(0)
),/* DMSFC */

(DMA_AdrPtr)MCBSP_ADDR(DRR10),/* DMSRC */
(DMA_AdrPtr)&dmaInbuff[0],/* DMDST */
(Uint16)(N)/* DMCTR = buffsize */
};

my_dmaCH2 = DMA_open(DMA_CHA2, 0);
DMA_config(my_dmaCH2, &dmaConfigCH2);

}
	void McBSP0_init(void)
{
// 54CST MCBSP does not have ABIS support
mcbspCFG0.spcr1 = MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,					
MCBSP_SPCR1_RJUST_DEFAULT,				
MCBSP_SPCR1_CLKSTP_DISABLE,				
MCBSP_SPCR1_DXENA_DEFAULT,				
//MCBSP_SPCR1_RINTM_RRDY,				
MCBSP_SPCR1_RINTM_FRM,					
MCBSP_SPCR1_RRST_DISABLE				
);/* SPCR1 */

mcbspCFG0.spcr2 MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,					
MCBSP_SPCR2_SOFT_NO,							
0x0001u,		
0x0000u,
MCBSP_SPCR2_XINTM_XRDY,					
MCBSP_SPCR2_XRST_DISABLE				
);/* SPCR2 */

mcbspCFG0.rcr1 MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(31),				
MCBSP_RCR1_RWDLEN1_8BIT					
);/* RCR1  */

mcbspCFG0.rcr2 MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,				
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_DEFAULT,
MCBSP_RCR2_RCOMPAND_DEFAULT,
//MCBSP_RCR2_RFIG_NO,
MCBSP_RCR2_RFIG_DEFAULT,
MCBSP_RCR2_RDATDLY_0BIT
);/* RCR2  */

mcbspCFG0.xcr1 MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(31),				
MCBSP_XCR1_XWDLEN1_8BIT					
);/* XCR1  */

mcbspCFG0.xcr2 MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,				
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_DEFAULT,
MCBSP_XCR2_XCOMPAND_DEFAULT,
//MCBSP_XCR2_XFIG_NO,
MCBSP_XCR2_XFIG_DEFAULT,
MCBSP_XCR2_XDATDLY_0BIT
);/* XCR2  */

mcbspCFG0.srgr1 MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0),					
MCBSP_SRGR1_CLKGDV_OF(0)				
);/* SRGR1 */

mcbspCFG0.srgr2 MCBSP_SRGR2_RMK(			
MCBSP_SRGR2_GSYNC_SYNC,					
MCBSP_SRGR2_CLKSP_RISING,				
MCBSP_SRGR2_CLKSM_CLKS,					
MCBSP_SRGR2_FSGM_DEFAULT,
MCBSP_SRGR2_FPER_OF(0)					
);/* SRGR2 */

mcbspCFG0.pcr MCBSP_PCR_RMK(
MCBSP_PCR_XIOEN_DEFAULT,			
MCBSP_PCR_RIOEN_DEFAULT,			
MCBSP_PCR_FSXM_DEFAULT,
MCBSP_PCR_FSRM_INTERNAL,			
MCBSP_PCR_CLKRM_OUTPUT,				
MCBSP_PCR_SCLKME_1,            
MCBSP_PCR_FSXP_DEFAULT,
MCBSP_PCR_FSRP_ACTIVELOW,			
MCBSP_PCR_CLKXP_RISING,          	
MCBSP_PCR_CLKRP_RISING			
);/* PCR */

myhMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
MCBSP_config(myhMcbsp0, &mcbspCFG0);

} //END OF init_McBSP0