HI Henrry,
> This EDMA parameter was working. But in my
opition, this
> configuration is not well optimized. Cause the EDMA transfer will
Yes.
On C64x (but probably valid also for C6711), the EDMA
controller need around 30 CPU cycles to schedule its
1st read transfer from the time it receive the
triggering event.
And you may still have to add a few delay to gain the bus
if the burst of another transfer is already performing
on the bus (EDMA/CPU priority scheduling is done on burst
frontiers).
So clearly, triggering the EDMA at byte level is not
a good idea.
As you have a frame buffer, I believe that you can
start reading the frame when the frame data is all
in the frame buffer so you won't have any synchronization
problems with the capture process : you can read as fast
as you can as all the datas already in frame buffer.
But the problem is that EDMA always require a
synchronization : either Frame or Element in 1D
mode. In 2D, it is Array or Block.
So if you want to use a N x M transfer in a single
EDMA request, without using partial sync event, you must
use a 2D transfer, Block Synchronized.
I must admit that for me too it is always tricky to
choose between 1D/2D, block/array, etc..
so I have a little test program (see it included).
For me the configuration that match your need
is :
EDMA_configArgs(
hEdma, // hEdma,
EDMA_OPT_RMK( // opt,
EDMA_OPT_PRI_HIGH, //pri,
EDMA_OPT_ESIZE_8BIT, //esize,
// Source is an single address( hardware port, fifo)
EDMA_OPT_2DS_NO, //ds2,
EDMA_OPT_SUM_NONE, //sum,
EDMA_OPT_2DD_YES, //dd2,
EDMA_OPT_DUM_INC, //dum,
EDMA_OPT_TCINT_YES, //tcint,
EDMA_OPT_TCC_OF(tcc), //tcc,
EDMA_OPT_LINK_NO, //link,
EDMA_OPT_FS_YES //fs
),
EDMA_SRC_RMK( Source ), //src,
EDMA_CNT_RMK( // cnt,
DEST_HEIGHT-1, // frmcnt,
DEST_WIDTH // elecnt
),
EDMA_DST_RMK( Dest ), //dst,
EDMA_IDX_RMK( //idx,
0, //frmidx,
0 //eleidx
),
EDMA_RLD_RMK( // rld
0, //elerld,
0 //link
)
);
> I still other thing that I am not well understand
about the EDMA
> when using 1D or 2D. When I was using 1D-1D (FS=0), the signal
> of /ARE will only have one clock cycle (LOW). But when I was using
> 1D-2D(FS=1) the /ARE signal will have two clock cycle in LOW (LOW-
> HIGH-LOW). Do you know what is the two clock cycle of LOW means ?
No idea yet.
I will ask to a hardware guru.
Jean-Michel MERCIER
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