> Jerry Avins <jya@ieee.org> wrote in message news:<4145efd4$0$2659$61fed72c@news.rcn.com>...
>
>>picnic wrote:
>>
>> ...
>>
>>
>>>So, after four samples, with four 1s and/or zeros coming in, your
>>>"filter" output (remember we are summing) can be either 000, 001, 010,
>>>011 or 100 (binary).
>>
>>Almost correct. You have 5 values there. The possible output can be 00,
>>01, 10, or 11. To get 3 bits, you would need to accumulate 8 samples.
>>
>> ...
>>
>>Jerry
>
>
> Okay...
>
> So, let's say we are accumulating FOUR values, and they are all ones:
>
> After sample #1: Sum = 1
> After sample #2: Sum = 10
> After sample #3: Sum = 11
> After sample #4: Sum = 100
>
> That looks a lot like three bits to me.

You're right. Something is a bit amiss, though. First off, if we're
going to use three bits, we might as well count up to seven. Another
issue troubles me more. I think it's a case of a carry bit, but that
could be a silly way to put it. If the count were sixteen, five bits
would be needed, and 15 out of a possible 32 numbers would go unused.
That's too dumb to live long. Someone must have invented a better way.
Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Reply by picnic●September 16, 20042004-09-16

Jerry Avins <jya@ieee.org> wrote in message news:<4145efd4$0$2659$61fed72c@news.rcn.com>...

> picnic wrote:
>
> ...
>
> > So, after four samples, with four 1s and/or zeros coming in, your
> > "filter" output (remember we are summing) can be either 000, 001, 010,
> > 011 or 100 (binary).
>
> Almost correct. You have 5 values there. The possible output can be 00,
> 01, 10, or 11. To get 3 bits, you would need to accumulate 8 samples.
>
> ...
>
> Jerry

Okay...
So, let's say we are accumulating FOUR values, and they are all ones:
After sample #1: Sum = 1
After sample #2: Sum = 10
After sample #3: Sum = 11
After sample #4: Sum = 100
That looks a lot like three bits to me.

Reply by hswnetin●September 14, 20042004-09-14

Hi All,
Thanks for your replies. I will consider all your inputs for my
groundwork. I will come back to you when I arrive at some stage of
design.
Thanks again to all of you.
Regards,
hswnetin
Jerry Avins <jya@ieee.org> wrote in message news:<4145efd4$0$2659$61fed72c@news.rcn.com>...

> picnic wrote:
>
> ...
>
> > So, after four samples, with four 1s and/or zeros coming in, your
> > "filter" output (remember we are summing) can be either 000, 001, 010,
> > 011 or 100 (binary).
>
> Almost correct. You have 5 values there. The possible output can be 00,
> 01, 10, or 11. To get 3 bits, you would need to accumulate 8 samples.
>
> ...
>
> Jerry

Reply by Jerry Avins●September 13, 20042004-09-13

picnic wrote:
...

> So, after four samples, with four 1s and/or zeros coming in, your
> "filter" output (remember we are summing) can be either 000, 001, 010,
> 011 or 100 (binary).

Almost correct. You have 5 values there. The possible output can be 00,
01, 10, or 11. To get 3 bits, you would need to accumulate 8 samples.
...
Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Reply by picnic●September 13, 20042004-09-13

hswnetin@yahoo.com (hswnetin) wrote in message news:<a4d4dd49.0409100158.333eb072@posting.google.com>...

> Hi All,
>
> I thank all of you, for your support, which I got previously. I am
> hardware design engineer and working on sigma delta ADC. And my role
> is to design decimation filter, basically I have to design a blocks
> which converts single bit to multi bits output. I surveyed lots of
> literature.
>
> I referred "An Economical Class of Digital Filters for Decimation and
> Interpolation" by Eugine B Hogenauer too. I could able to understand
> the following things like, decimator receives single bit (or 2 or 3
> bit output depending on modulator). And there are integrator stage and
> comb stage. etc. I am unable to understand how the single bit is
> converted to multi bits. I could not understand the concept of number
> of stages. Also I could not understand the logic behind dropping of
> bits after calculating the Bmax.
>
> Please help me in understanding the issues in decimator filter.
>
> Thanks in advance.
>
> Regards,
> hswnetin

Maybe a trivially simple example can help:
Let's say your "filter" is just accumulating the bit stream.
Let's also say your decimation factor is four - meaning you are
sampling the "filter" (accumulator) output four times slower that the
filter input rate.
So, after four samples, with four 1s and/or zeros coming in, your
"filter" output (remember we are summing) can be either 000, 001, 010,
011 or 100 (binary).
So, you can see that your one bit of INPUT resolution has magically
increased to three bits of OUTPUT resolution!
Basically, you use many tiny values over time to make one big value.
Does that help or is it too simplistic?

Reply by Jerry Avins●September 13, 20042004-09-13

Randy Yates wrote:

> Jerry Avins <jya@ieee.org> writes:
>
>
>>Randy Yates wrote:
>>
>>
>>> ... If the output values are asymmetrical (e.g., 0/1), then
>>>you will have a DC offset, but that's not relevent to the upper part of the
>>>spectrum where the quantization noise will be.
>>
>>Hmmm... If there are no transitions at all, there will be lots of DC
>>offset and no noise at all. Something doesn't hang together and at the
>>moment, I don't see what.
>
>
> Jerry,
>
> If there are no transitions at all, then the input must be precisely
> at one of the two binary output levels, thus the output is following
> the input exactly and in this case there is no quantization noise.
>
> When the input moves off of either of the two binary output values,
> then the modulator will start "modulating," i.e., moving back and
> forth between the two output values in a manner such that the average
> output value equals the input value.
>
> Doesn't that hang together perfectly?

It does. I'm not sure how it ties in with the high-frequency noise being
independent of the DC offset. I accept my "counterexample" as an
exceptional case.
Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Reply by ●September 13, 20042004-09-13

Randy Yates <randy.yates@sonyericsson.com> writes:

> [blah blah blah]

Wait. I think maybe I see the unhanging you (Jerry) spoke of
now.
I brought up a bastard case - one in which there are two
outputs from the quantizer. One output feeds the summing junction
at the front-end and must be "correct" (e.g., 0x7FFF and
0x8001, in two's complement). However, note that this output is
"multibit" even though there are only two values used. Herein
lies the (potential) confusion - many folks take the MSB (the
sign) bit can call *THAT* the output (e.g., for input to a Matlab
routine). Then THAT output will have a DC offset that is not "really"
there.
That's the scenario I meant to address, in any case.
--
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124

Reply by ●September 13, 20042004-09-13

Jerry Avins <jya@ieee.org> writes:

> Randy Yates wrote:
>
> > ... If the output values are asymmetrical (e.g., 0/1), then
> > you will have a DC offset, but that's not relevent to the upper part of the
> > spectrum where the quantization noise will be.
>
> Hmmm... If there are no transitions at all, there will be lots of DC
> offset and no noise at all. Something doesn't hang together and at the
> moment, I don't see what.

Jerry,
If there are no transitions at all, then the input must be precisely
at one of the two binary output levels, thus the output is following
the input exactly and in this case there is no quantization noise.
When the input moves off of either of the two binary output values,
then the modulator will start "modulating," i.e., moving back and
forth between the two output values in a manner such that the average
output value equals the input value.
Doesn't that hang together perfectly?
--
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124

Reply by Jerry Avins●September 13, 20042004-09-13

Randy Yates wrote:

> ... If the output values are asymmetrical (e.g., 0/1), then
> you will have a DC offset, but that's not relevent to the upper part of the
> spectrum where the quantization noise will be.

Hmmm... If there are no transitions at all, there will be lots of DC
offset and no noise at all. Something doesn't hang together and at the
moment, I don't see what.
Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

Reply by ●September 13, 20042004-09-13

hswnetin@yahoo.com (hswnetin) writes:

> Hi All,
>
> Thanks for your replies. Now I will do little groundwork on analysis
> in frequency domain. I will work on it, if i am not clear at any
> point, I will post to group again. Before this can anyone tell me
> about the spectrum of modulator output? Is it possible to see the
> spectrum of output of the modulator? How to see the spectrum using
> MATLAB? My basic doubt is producing the spectrum using single bit
> data.
>
> Please help me in this regard.
>
> Thanks and regards,
> hswnetin

Hi hswnetin,
You can examine the spectrum of the one-bit modulator output in Matlab.
If x is a vector of the modulator output values, then one way to examine
the spectrum in Matlab is via "psd(x)".
Note that since the modulator output is one bit, the elements of x will take
on only two different values (e.g., +1/-1, 0x7FFF/0x80001, etc.). That's OK
to input into the psd() routine and should give you exactly the spectrum
you want to examine. If the output values are asymmetrical (e.g., 0/1), then
you will have a DC offset, but that's not relevent to the upper part of the
spectrum where the quantization noise will be.
--
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124