Hi, Andor,
--- andor_bariska <> wrote:
> Hi all,
>
> I'm getting some unexpected results from the
> following setup, and
> perhaps someone has an idea why.
>
> I am simulating a 65L program. The simulator uses
> SPORTs streaming to
> read data from a file. The DMA reads a block of data
> (say 80 32bit
> words), then an interrupt occrus. In the meantime,
> DMA chain loading
> occurs and to initialize another DMA, which again
> reads 80 values,
> this time into a second buffer. The two buffers are
> continuously
> filled by alternating DMAs. There is no other DMA
> activity.
>
> I have set the SPORT input divisor to read a value
> every 1248
> processor cycles (RDVI = 0x26).
>
> This works most of the time.
>
> However, for some transfers, I'm seeing a much
> larger cycle count
> between reading two consecutive values from the
> SPORT (up to about
> 2000 cycles). This is odd: since I have an internal
> SPORT clock, this
> shouldn't happen. The data should be read at a
> constant rate.
>
> I'm seeing the prolonged cycle counts especially
> when heavy usage is
> made with simultaneous PM and DM reads, as well as
> during 16bit
> internal memory accesses.
Have you checked that the PM and DM, and 16 bit
internal memory accesses are being executed in
parallel with other operations, when coded to do so? I
mean, is there any possibility that for some
instructions the processor is not executing in a
single cycle?
JaaC
>
> Has somebody experienced similar behaviour or can
> explain why I'm
> having irregular cycle counts between internally
> clocked SPORT DMA
> accesses?
>
> Regards,
> Andor
>
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