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Hi N. Janarthanan. The reset value at 0x0 is a 32 bit starting *address* or vector, not an (branch) instruction. On reset the CPU reads this value and stuffs it directly into the program counter pipeline. A few cycles later, execution begins with a program fetch at that address. The next few locations are interrupt and trap vectors and work the same way. When the interrupt/reset pin (think of reset as a non maskable interrupt) is asserted, a read is made at the appropriate vector to read an *address* that is then stuffed into the program counter. You will also notice an MCBL/MP pin. This is really nothing more than external/internal memory select pin. If MCBL=0, resets and interrupts are made to external memory. If MCBL=0 the internal (boot)ROM is enabled and vector fetches are made to internal memory. Therefor, if MCBL=0 you *must* have some kind of external memory to fetch a reset or interrupt vector from. In the bad old days, before there was an internal boot rom, this meant an external 32b wide ROM mapped to 0x0. This ROM also typically contained the users application code in 32b executable form. In a more modern configuration the boot rom is enabled (MCBL=1) allowing the DSP to fetch a reset vector from the internal ROM and begin execution... where you might ask? Why from internal ROM of course. Not only does the internal ROM hold reset and interrupt vectors, but it also contains a small loader program. The loader program, better known as the BOOTLOADER program, can be found in the back of the C3x users guide. So what does the bootloader do? First, it polls the remaining INTx lines to see which ones are high or low. NOTE: This is NOT an interrupt routines. From this, the bootloader has the information it needs to know where the users external BOOT program ROM is located. Next, the bootloader reads the first location to see how many bits wide the external ROM is. Typically a low cost 8b ROM is used, which is of no use to run code from, so the bootloader then needs to read 32b values from the ROM in 4x8 bit chunks, that are then placed into a destination location. Again, read the bootloader section in the users guide to get an idea how this works. Hope this helps Best regards Keith Larson DSP and Analog Consulting Lincoln, Ma Additional Info: If MCBL=1 (using the bootloader) you may begin to wonder how you can define where an interrupt vector should begin execution. After all, with MCBL=1 the internal ROM is enabled and you cant change the contents of a Read Only Memory! So where do you think the interrupt vectors point to? Hint... many cheapy systems dont have external RAM so this would not make any sense. ---- janarthanan n wrote: Dear sir, I am doing a project using DSPc3x interfaced with SRAM. I came through a problem while using C3x processor without using emulator to Download the program to DSP. What steps i have to take for Boot Loading Program?(I am just writing my program hex code to program memory). Whether i have leave the memory location 0h(Reset location) as it is or i have to write any jump instruction? Please guide me on this issue. N.Janarthanan |