Brandon, I'm using 3-way L2 and -ml2 compilation option and I haven't seen this particular problem. Of course that doesn't help you too much. Are you using EDMA at all ? It so, maybe there are some cache clean calls required. Andrew At 11:51 AM 2/7/01 -0600, Brandon Eames wrote: >Hello, > >We are developing a fairly large application using a C6711. We are trying >to utilize both levels of cache in our implementation. We have the L2 >configured to be 1/2 cache and 1/2 SRAM. Our architecture is such that we >require the large memory model, so we are compiling our runtime system and >our components with the -ml3 option. Compilation with this option generates >a .far section to be mapped to a particular location in the memory map by >the linker. The problem we experience is that when we have our MAR >registers set such that the area of memory which contains the .far section >is cached, the program hangs. We moved the .far section to another memory >bank, and observed similar results. Does anyone know about any issues >surrounding the caching of the .far section? >Thanks, > >Brandon Eames > > >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of >this message will receive your answer. You need to do a "reply all" if you >want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.egroups.com/group/c6x > >Other Groups: http://www.dsprelated.com > Regards Andrew Elder ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ AudioScience, Inc. (Rochester Branch) 116 Corwin Rd., Rochester, NY 14610 ph (1) (716) 224 9027 fax (1) (412) 291 1111 <www.audioscience.com> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |