Reply by Randy Yates September 25, 20152015-09-25
Rob Gaddi <rgaddi@technologyhighland.invalid> writes:

> On Wed, 23 Sep 2015 20:21:33 -0400, Randy Yates wrote: > >> Rob Gaddi <rgaddi@technologyhighland.invalid> writes: >> >>> Got an application coming up for a high-efficiency, multikilowatt >>> polyphase power supply that needs scarily fast responses to external >>> requests. I'm thinking about maybe throwing a C2000 at the problem. >>> It could really simplify keeping my phases in alignment and getting the >>> feedforward through all the paths to match. >>> >>> TI sure makes it look easy, almost as if it's their job to do so. >>> Anyone got any stories to share from that war? >> >> PS: Rob, are you considering using GaN devices? Aren't they known >> (basically) for their low on-resistance and high switching rates? > > We gave it some thought, but for a 1 MHz sort of switch rate silicon's > still fine. We've done some experiments with GaN in the far distant > past, but found it to be easy to damage. Plus any time I can leave > exotica off the BOM I'm happier. > > Granted that was all before TI got into the game which definitely changes > things. Again, we didn't get particularly far into this process before > it changed direction.
Interesting to hear anyway of your thought processes. Thanks. -- Randy Yates Digital Signal Labs http://www.digitalsignallabs.com
Reply by rickman September 24, 20152015-09-24
On 9/24/2015 1:59 PM, Tim Wescott wrote:
>>>> >>> that's not what he wrote, >>> >>> x cost X, y cost Y, but if y wasn't build x could be sold for Z >>> >>> only one chip need to be designed, everyone saves money and those who >>> doesn't need the extra stuff can ignore it >> >> That's my point. His example doesn't include the case of just building >> Y and no X or Z. > > X, Y and Z are dollar amounts. Do you understand this discussion?
Really? You can't figure out what I'm saying???
>> X has the extra hard logic and Y can be built for less >> than any of the above. > > And (assuming you mean x and y), all the people who did want that hard IP > start buying their chips from someone else, and the executive who decided > not to make x gets the opportunity to be in charge of marketing for some > other company.
We are talking about the reason for including all the hard IP. I didn't say it wasn't a good idea. I said it wasn't because of the reasoning you offer. Someone else in this thread gave the real reason for it and I have already acknowledged that. -- Rick
Reply by Rob Gaddi September 24, 20152015-09-24
On Thu, 24 Sep 2015 13:14:13 -0500, Tim Wescott wrote:

> On Wed, 23 Sep 2015 18:35:10 -0400, robert bristow-johnson wrote: > >> On 9/23/15 5:40 PM, Tim Wescott wrote: >>> >>> Rob mentions elsewhere that he's looking at a 1MHz sampling rate >> >> can someone explain why or what the device is that draws power from >> some DSP-controlled power source (say PWM or PDM, which seems to me to >> be about the same as sigma-delta) that needs a sample rate of 1MHz? > > God only knows. But DSP chips are being used in honkin' big switching > power supplies these days because you can do more sophisticated control > in a smaller space than you can with all analog circuitry. > > In this case the "PWM" that's being talked of is going straight to the > gates of some honkin' big power transistors that are then steering > (possibly) kW of power. > >>> and a 20us ramp from zero to full-on. >> >> >> i fail to see why that ramp needs to be sampled 20 times from zero to >> rails. > > As a rule of thumb in digital control systems, the settling time from > the point where the system comes out of severely nonlinear operation to > the point where it's "settled" ("settled" has more than one meaning, but > -- more or less stopped). > > Since the overall settling time is set at 20us, 1MHz is a good starting > point for the sampling time of the control system. > >> i admit that i am outa my element, but i'm having trouble visualizing >> this. what power controller needs such a spec? what's it powering? > > God knows, but apparently it needs to start with a jolt! > > That's a good point -- Rob may want to question the customer to verify > that the thing really needs to start that fast. >
Customer wants to be able to turn this thing on and off at up to 5 kHz, so with even 20 us edges it's getting pretty trapezoidal. Now, why THAT part is necessary is beyond me, though we've finally got an NDA down so at least my curiosity can be abated, even if I can't share. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
Reply by Tim Wescott September 24, 20152015-09-24
On Thu, 24 Sep 2015 13:22:16 -0400, Randy Yates wrote:

> makolber@yahoo.com writes: > > >>> > Thus you have the classic engineering tradeoff: given a fixed >>> > T_{SYSCLK} >>> > you want to increase T_{PWM} to improve the number of bits, but you >>> > want to decrease T_{PWM} to increase the sample rate. Or viewed >>> > another way, you have to have a low T_{SYSCLK} if you simultaneously >>> > want a high sample rate and more bits. >>> >> Why would you even want to use a true digital feedback loop? >> >> Why not a tight analog feedback loop and you can hang ADCs and DACs on >> it to monitor and control it if you wish. Use a DAC to set the >> setpoint and an ADC to monitor the output. Trim the setpoint from time >> to time as needed. Even change the loop gain and BW if you wanted to >> go nuts. > > I guess for all the usual reasons you use digital over analog: immunity > to component tolerance and variance with age/temperature, better noise > immunity, easier to control, etc. You can achieve these things in analog > too, but it is usually harder. But whatever floats your boat and gets > the job done.
Harder and bigger (there's a double entendre in there, I know there is). There's a line that's roughly determined by speed / complexity that separates problems that are favorable to do in analog from problems that are favorable to do in digital -- that line has been steadily moving more and more toward "digital" for my entire career, and shows no signs of stopping. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Tim Wescott September 24, 20152015-09-24
On Thu, 24 Sep 2015 00:09:28 -0400, Randy Yates wrote:

> Randy Yates <yates@digitalsignallabs.com> writes: > >> Randy Yates <yates@digitalsignallabs.com> writes: >> >>> robert bristow-johnson <rbj@audioimagination.com> writes: >>> >>>> On 9/23/15 5:40 PM, Tim Wescott wrote: >>>>> On Wed, 23 Sep 2015 14:28:52 -0700, gyansorova wrote: >>>>> >>>>>> On Tuesday, September 22, 2015 at 6:51:30 AM UTC+12, Rob Gaddi >>>>>> wrote: >>>>>>> Got an application coming up for a high-efficiency, multikilowatt >>>>>>> polyphase power supply that needs scarily fast responses to >>>>>>> external requests. I'm thinking about maybe throwing a C2000 at >>>>>>> the problem. It could really simplify keeping my phases in >>>>>>> alignment and getting the feedforward through all the paths to >>>>>>> match. >>>>>>> >>>>>>> TI sure makes it look easy, almost as if it's their job to do so. >>>>>>> Anyone got any stories to share from that war? >>>>>>> >>>>>>> -- >>>>>>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email >>>>>>> address domain is currently out of order. See above to fix. >>>>>> >>>>>> I think you need FPGAs. You will always have nano seconds latency >>>>>> since your code executes serially. >>>>> >>>>> Rob mentions elsewhere that he's looking at a 1MHz sampling rate >>>> >>>> can someone explain why or what the device is that draws power from >>>> some DSP-controlled power source (say PWM or PDM, which seems to me >>>> to be about the same as sigma-delta) that needs a sample rate of >>>> 1MHz? >>>> >>>>> and a 20us ramp from zero to full-on. >>>> >>>> >>>> i fail to see why that ramp needs to be sampled 20 times from zero to >>>> rails. >>>> >>>> i admit that i am outa my element, but i'm having trouble visualizing >>>> this. what power controller needs such a spec? what's it powering? >>>> >>>> is it step response envelope delay? >>> >>> Hey Robert, >>> >>> Blind leading the blind but here goes... >>> >>> It's a feedback control system. If the desired step response is 20 >>> microseconds, you need to be sampling the output a good bit faster and >>> running that through your feedback loop. There's also the issue of >>> latency - you always want to minimize latency in order to improve >>> stability - and increasing the sample rate, even if you don't need the >>> bandwidth, is a way to reduce latency in a sampled control system. >>> >>> If you're like me, the barrage of terms is also confusing. To help >>> with that, you can look at the reference guide I was referring to in >>> another post, the TI SPRUG77B on their "high-resolution pulse width >>> modulator" in the Delfino series (TMS320x2834x). Figure 1 there shows >>> a nice, basic picture of the PWM signal and it's parameters. >>> >>> T_{PWM} there is what has been called here in various posts as the >>> "sample rate" and "switching frequency." The T_{SYSCLK} is the >>> parameter Rob was referring to when he mentioned 150ps. >>> >>> Rob, Tim, Rick, whoever, correct me if I got something wrong here. >> >> ...continued... >> >> http://www.ti.com.cn/general/cn/docs/lit/getliterature.tsp?
baseLiteratureNumber=sprug77&fileType=pdf
>> >> You can see from the "PWM resolution (bits)" there that the number of >> bits increases as T_{SYSCLK} decreases (higher frequency) and T_{PWM} >> increases (lower frequency). >> >> Thus you have the classic engineering tradeoff: given a fixed >> T_{SYSCLK} >> you want to increase T_{PWM} to improve the number of bits, but you >> want to decrease T_{PWM} to increase the sample rate. Or viewed another >> way, you have to have a low T_{SYSCLK} if you simultaneously want a >> high sample rate and more bits. > > Q: Does the sample rate of the ADC (providing the feedback for the > closed loop) have to be the same as the switching frequency (T_{PWM})?
No. It can be either higher or lower, depending on the application. In Rob's case you may actually want to have it higher, because it's a polyphase system. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Tim Wescott September 24, 20152015-09-24
On Thu, 24 Sep 2015 06:14:30 -0700, makolber wrote:


>> > Thus you have the classic engineering tradeoff: given a fixed >> > T_{SYSCLK} >> > you want to increase T_{PWM} to improve the number of bits, but you >> > want to decrease T_{PWM} to increase the sample rate. Or viewed >> > another way, you have to have a low T_{SYSCLK} if you simultaneously >> > want a high sample rate and more bits. >> > Why would you even want to use a true digital feedback loop? > > Why not a tight analog feedback loop and you can hang ADCs and DACs on > it to monitor and control it if you wish. Use a DAC to set the setpoint > and an ADC to monitor the output. Trim the setpoint from time to time > as needed. Even change the loop gain and BW if you wanted to go nuts.
You want a true digital feedback loop in a switcher for the same reason you do anywhere else: because unless you're doing something really simple, you can get more performance in less space with a digital controller. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Tim Wescott September 24, 20152015-09-24
On Wed, 23 Sep 2015 19:59:51 -0400, Randy Yates wrote:

> robert bristow-johnson <rbj@audioimagination.com> writes: > >> On 9/23/15 5:40 PM, Tim Wescott wrote: >>> On Wed, 23 Sep 2015 14:28:52 -0700, gyansorova wrote: >>> >>>> On Tuesday, September 22, 2015 at 6:51:30 AM UTC+12, Rob Gaddi wrote: >>>>> Got an application coming up for a high-efficiency, multikilowatt >>>>> polyphase power supply that needs scarily fast responses to external >>>>> requests. I'm thinking about maybe throwing a C2000 at the problem. >>>>> It could really simplify keeping my phases in alignment and getting >>>>> the feedforward through all the paths to match. >>>>> >>>>> TI sure makes it look easy, almost as if it's their job to do so. >>>>> Anyone got any stories to share from that war? >>>>> >>>>> -- >>>>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email >>>>> address domain is currently out of order. See above to fix. >>>> >>>> I think you need FPGAs. You will always have nano seconds latency >>>> since your code executes serially. >>> >>> Rob mentions elsewhere that he's looking at a 1MHz sampling rate >> >> can someone explain why or what the device is that draws power from >> some DSP-controlled power source (say PWM or PDM, which seems to me to >> be about the same as sigma-delta) that needs a sample rate of 1MHz? >> >>> and a 20us ramp from zero to full-on. >> >> >> i fail to see why that ramp needs to be sampled 20 times from zero to >> rails. >> >> i admit that i am outa my element, but i'm having trouble visualizing >> this. what power controller needs such a spec? what's it powering? >> >> is it step response envelope delay? > > Hey Robert, > > Blind leading the blind but here goes... > > It's a feedback control system. If the desired step response is 20 > microseconds, you need to be sampling the output a good bit faster and > running that through your feedback loop. There's also the issue of > latency - you always want to minimize latency in order to improve > stability - and increasing the sample rate, even if you don't need the > bandwidth, is a way to reduce latency in a sampled control system. > > If you're like me, the barrage of terms is also confusing. To help with > that, you can look at the reference guide I was referring to in another > post, the TI SPRUG77B on their "high-resolution pulse width modulator" > in the Delfino series (TMS320x2834x). Figure 1 there shows a nice, basic > picture of the PWM signal and it's parameters. > > T_{PWM} there is what has been called here in various posts as the > "sample rate" and "switching frequency." The T_{SYSCLK} is the parameter > Rob was referring to when he mentioned 150ps. > > Rob, Tim, Rick, whoever, correct me if I got something wrong here.
Not wrong, per se., but not complete. Switching frequency is how rapidly you switch the transistors. The control system sampling rate can be lower (or, in the case of a polyphase system) higher than the switching frequency. As an example, I've got a motor control board that switches at 10kHz, but, to reduce computation load, samples the control system at 5kHz. This means that the control loop sets the PWM duty cycle for two PWM cycles, then repeats. A polyphase switcher has multiple drive stages that are operating in a staggered arrangement. So if you have four output stages, and if you can sample the output voltage and change the duty cycle of individual stages independently enough, then you could actually sample the control system at four times the switch rate. You're correct about latency and bandwidth. The Nyquist limit makes sense in a system where you just want to reconstruct a signal later. In a closed-loop system, the latency affects the amount of phase lag in the controller, and it is phase lag that is one of the most significant drivers to control loop performance. In an ideal world you arrange for a sampling rate that is high enough that the lag from sampling is insignificant compared to the lag from the plant itself. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Tim Wescott September 24, 20152015-09-24
On Wed, 23 Sep 2015 18:35:10 -0400, robert bristow-johnson wrote:

> On 9/23/15 5:40 PM, Tim Wescott wrote: >> On Wed, 23 Sep 2015 14:28:52 -0700, gyansorova wrote: >> >>> On Tuesday, September 22, 2015 at 6:51:30 AM UTC+12, Rob Gaddi wrote: >>>> Got an application coming up for a high-efficiency, multikilowatt >>>> polyphase power supply that needs scarily fast responses to external >>>> requests. I'm thinking about maybe throwing a C2000 at the problem. >>>> It could really simplify keeping my phases in alignment and getting >>>> the feedforward through all the paths to match. >>>> >>>> TI sure makes it look easy, almost as if it's their job to do so. >>>> Anyone got any stories to share from that war? >>>> >>>> -- >>>> Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email >>>> address domain is currently out of order. See above to fix. >>> >>> I think you need FPGAs. You will always have nano seconds latency >>> since your code executes serially. >> >> Rob mentions elsewhere that he's looking at a 1MHz sampling rate > > can someone explain why or what the device is that draws power from some > DSP-controlled power source (say PWM or PDM, which seems to me to be > about the same as sigma-delta) that needs a sample rate of 1MHz?
God only knows. But DSP chips are being used in honkin' big switching power supplies these days because you can do more sophisticated control in a smaller space than you can with all analog circuitry. In this case the "PWM" that's being talked of is going straight to the gates of some honkin' big power transistors that are then steering (possibly) kW of power.
>> and a 20us ramp from zero to full-on. > > > i fail to see why that ramp needs to be sampled 20 times from zero to > rails.
As a rule of thumb in digital control systems, the settling time from the point where the system comes out of severely nonlinear operation to the point where it's "settled" ("settled" has more than one meaning, but -- more or less stopped). Since the overall settling time is set at 20us, 1MHz is a good starting point for the sampling time of the control system.
> i admit that i am outa my element, but i'm having trouble visualizing > this. what power controller needs such a spec? what's it powering?
God knows, but apparently it needs to start with a jolt! That's a good point -- Rob may want to question the customer to verify that the thing really needs to start that fast.
> is it step response envelope delay?
Envelope delay isn't a concept that finds its way into control systems, much. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Tim Wescott September 24, 20152015-09-24
On Wed, 23 Sep 2015 22:02:21 -0400, rickman wrote:

> On 9/23/2015 7:22 PM, lasselangwadtchristensen@gmail.com wrote: >> Den onsdag den 23. september 2015 kl. 21.16.36 UTC+2 skrev rickman: >>> On 9/23/2015 2:50 PM, Tim Wescott wrote: >>>> On Wed, 23 Sep 2015 14:18:15 -0400, rickman wrote: >>>> >>>>> On 9/23/2015 1:42 PM, Tim Wescott wrote: >>>>>> On Tue, 22 Sep 2015 13:56:57 -0400, rickman wrote: >>>>>> >>>>>>> On 9/22/2015 1:46 PM, Tim Wescott wrote: >>>>>>>> On Tue, 22 Sep 2015 17:07:42 +0000, Rob Gaddi wrote: >>>>>>>> >>>>>>>>> On Tue, 22 Sep 2015 10:33:20 -0400, rickman wrote: >>>>>>>>> >>>>>>>>>> To date, the two large FPGA companies are sticking to the path >>>>>>>>>> that got them where they are, catering to the large comms >>>>>>>>>> companies needs which is bigger, faster FPGAs. There is a lot >>>>>>>>>> more margin at the high end than at the low end. Motor control >>>>>>>>>> would definitely be the low end. Someone has already complained >>>>>>>>>> about FPGA prices in this thread. >>>>>>>>>> >>>>>>>>>> There is nothing stopping FPGAs from being built like MCUs with >>>>>>>>>> all manner of accessories built in. But the big guys aren't >>>>>>>>>> going to do it. >>>>>>>>>> The new market for FPGAs is in very high volume handheld >>>>>>>>>> devices. >>>>>>>>>> The >>>>>>>>>> new push is to low end FPGAs in very small packages and price >>>>>>>>>> will be a major issue. So far there aren't many pushing in >>>>>>>>>> that direction. The processes are still digital. But once they >>>>>>>>>> broach this market more they will be more inclined to break out >>>>>>>>>> of their mold and explore more innovative areas like motor >>>>>>>>>> control with analog subsystems. >>>>>>>>> >>>>>>>>> Actually, both X and A have SoC offerings now that integrate ARM >>>>>>>>> Cortex A9s with a mess of peripherals alongside the fabric. >>>>>>>>> >>>>>>>>> I'm actually really surprised at the balance they struck; they >>>>>>>>> both decided to put a LOT of hard IP in. Gb Ethneret MAC, DRAM >>>>>>>>> controller, >>>>>>>>> all that stuff makes sense to me to harden. But they're also >>>>>>>>> putting SPI, I2C, counter/timers, all the sort of stuff that >>>>>>>>> seems like it would be just as easily implemented on the fabric. >>>>>>>>> Beats me what the logic was. >>>>>>>> >>>>>>>> You can implement stuff in much less space (and probably power) >>>>>>>> if it's hard-coded rather than implemented in the FPGA fabric -- >>>>>>>> that's why there's a processor core in there and not just >>>>>>>> available IP. The logic extends to peripherals: if it's >>>>>>>> something that's used a lot, then it's worthwhile putting in. I >>>>>>>> suspect that the area difference is 10:1, which would mean >>>>>>>> (roughly) that if you put in 10 different peripherals and each >>>>>>>> customer used one and let the other 9 lie idle, that you'd break >>>>>>>> even on area and come out ahead on power consumption. >>>>>>> >>>>>>> Saving area is only useful if you *use* the IP. >>>>>> >>>>>> No, saving area is only useful if it makes the chip less expensive >>>>>> or (assuming I care) consume less power. If 10 peripherals, >>>>>> together, are smaller and less expensive than the generic fabric I >>>>>> need to implement the one I actually use, then I don't give a crap >>>>>> about the unused 9 -- I'll just chortle happily every time I review >>>>>> the BOM. >>>>> >>>>> What does the BOM have to do with it? None of this will add any >>>>> parts or is at all likely to require a larger part. If this was the >>>>> guiding principle to adding hard IP, there would be a lot more hard >>>>> IP on a lot more FPGAs. >>>> >>>> Man, if I said "what does the BOM have to do with it" to a customer >>>> for whom I was designing a board, I would only have myself to blame >>>> if they hung up on me and expunged me from their files. >>>> >>>> BOM "has to do with it" because BOM cost matters. It just does. >>>> >>>>>> If I'm trying to minimize power consumption and the one peripheral >>>>>> I use takes 1/3 the power (I'm just inventing numbers in my head >>>>>> here, BTW) that I'd need to implement it in the fabric, then I may >>>>>> be willing to pay _more_ for the chip, even. >>>>>> >>>>>> So, I disagree. >>>>> >>>>> Trouble is all your numbers are made up and it assumes that all >>>>> designs using that FPGA will use *any* of the added hard IP. >>>> >>>> Well, yes, my numbers are made up, for illustrative purposes. I'm >>>> assuming that -- being an engineer -- you know how to get the gist of >>>> what I'm saying without getting hung up on the specific numbers. >>>> >>>> My point is made even if not all designs using an FPGA use any of the >>>> added IP. If Xilinx can make one chip with added hard IP for cheaper >>>> than it can make two chips, one with the added IP and one without, >>>> and if it passes that savings on to its customers, then the people >>>> who use the chips without ever turning on the hard IP benefit from >>>> having a chip to use in the first place. >>>> >>>> Since you don't want me to use made-up numbers, I'll just use >>>> inequalities. If X > Y > Z represent three dollar amounts, would you >>>> Xilinx sold chip x (with hard IP that you don't have to use) and chip >>>> y (without), at costs X and Y, or would you rather Xilinx sold only >>>> chip x at cost Z, or would you rather pay a premium for chip y so >>>> that you can use it without offending your sensibilities? >>> >>> Actually this is not the comparison. If chip Y is cheaper than chip >>> X and also cheaper than chip Z, then offer the SPI, I2C, etc as soft >>> IP and be done with it. Quit making stuff up! >>> >>> >> that's not what he wrote, >> >> x cost X, y cost Y, but if y wasn't build x could be sold for Z >> >> only one chip need to be designed, everyone saves money and those who >> doesn't need the extra stuff can ignore it > > That's my point. His example doesn't include the case of just building > Y and no X or Z.
X, Y and Z are dollar amounts. Do you understand this discussion?
> X has the extra hard logic and Y can be built for less > than any of the above.
And (assuming you mean x and y), all the people who did want that hard IP start buying their chips from someone else, and the executive who decided not to make x gets the opportunity to be in charge of marketing for some other company. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by Rob Gaddi September 24, 20152015-09-24
On Wed, 23 Sep 2015 20:21:33 -0400, Randy Yates wrote:

> Rob Gaddi <rgaddi@technologyhighland.invalid> writes: > >> Got an application coming up for a high-efficiency, multikilowatt >> polyphase power supply that needs scarily fast responses to external >> requests. I'm thinking about maybe throwing a C2000 at the problem. >> It could really simplify keeping my phases in alignment and getting the >> feedforward through all the paths to match. >> >> TI sure makes it look easy, almost as if it's their job to do so. >> Anyone got any stories to share from that war? > > PS: Rob, are you considering using GaN devices? Aren't they known > (basically) for their low on-resistance and high switching rates?
We gave it some thought, but for a 1 MHz sort of switch rate silicon's still fine. We've done some experiments with GaN in the far distant past, but found it to be easy to damage. Plus any time I can leave exotica off the BOM I'm happier. Granted that was all before TI got into the game which definitely changes things. Again, we didn't get particularly far into this process before it changed direction. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.