Guo,
The ESAI_1 control registers are in YRAM I/O space, not XRAM I/O...
--
dB
--- "Corey, Rick" <rcorey@rcor...> wrote:
>
>
> -----Original Message-----
> From: ʿ [mailto:gybbh@gybb...]
> Sent: Tuesday, June 21, 2005 4:24 AM
> To: Michael.W.Mann@Mich...; wy_sx88@wy_s...;
> motoroladsp-owner@moto...
> Subject: The Problems about ESAI_1 Port of DSP563
> Dear Sir,
> I have some troubles about the usage of ESAI_1 port of DSP56367 when
> debug
> by JTAG !
> The ESAI_1 port cann't work. And the registers about ESAI_1 seems
> cann't
> access.
> I want to know if the registers about ESAI_1 can access in debug
> mode by
> JTAG.
> But the ESAI port can work well.
> Wish to write back soon.
> Thanks.
> The program is the following.
>
;**************************************************************************
> ;Motorola DSP56367 Audio.asm
> ;2005.6.20
> ;SDI0 receive IIS data through DMA0
> ;SDO4,5 Tranmit IIS data through DMA1
> ;gybbh@gybb...
;**************************************************************************
> include 'ioequ.asm'
;**************************************************************************
> org p:$100
> START
> main
> ori #$03,mr ; mask interrupts
> movep #$0620008,x:M_PCTL ;f=(Ef MF)/(PDF br />
> DF)$.567*10/22.835MHz
> ;clkout enable
> move #0,omr
> movec #0,sp ; reset hardware stack pointer
> movep #$000C03,x:M_IPRP ; ESAI and ESAI_1 ints enabled and top
> Priority
> move #$40,r6 ; initialize stack pointer
> bclr #0,r7 ; bit0 Receive Buffer Switch Flag(0:000-3ff; 1:400-7ff)
> ;; bit1 Transmit Buffer Switch Flag(0:800-bff; 1:c00-fff)
>
;**************************************************************************
> ; FST/FSR and SCKT/SCKR are generated from the
out
> ; and fed to the DSP
;**************************************************************************
> movep #$000000,x:M_PCRC ;disable ESAI port
> movep #$000000,x:M_PRRC
> movep #$000000,x:M_PCRE ;disable ESAI port
> movep #$000000,x:M_PRRE
> movep #$040200,x:M_TCCR ;init transmit clock control register
> movep #$840200,x:M_TCCR_1 ;init transmit clock control register
> ;THCKD=0 (bit23=0)
> ;FST is input (bit22=0)
> ;SCKT is driven externally (bit21=0)
> ;FST polarity is negative (bit19=1)
> ;clockout on falling, latch in on rising(bit18=0)
> ;2 words per frame (bit13:9001)
> ;all other bits are not relevant and are initialized to 0
> movep #$040200,x:M_RCCR ;init receive clock control register
> movep #$040200,x:M_RCCR_1 ;init receive clock control register
> ;RHCKD=0(SYN=0) HCKR -> input
> ;FSR is input (bit22=0)
> ;SCKR is driven externally (bit21=0)
> ;Receiver High Frequency Clock Polarity (NoUsed)
> ;FSR polarity is negative (bit19=0)
> ;clockout on falling, latch in on rising(bit18=1)
> ;2 words per frame (bit13:9001)
> ;all other bits are not relevant and are initialized to 0
> movep #$000000,x:M_SAICR ;init ESAI common control register
> movep #$000000,x:M_SAICR_1 ;init ESAI common control register
> ;data left aligned to bit 23 (bit8=0)
> ;asynchronous mode (bit6=0)
> ;bits 23:9 and 5:3 are reserved and are initialized to 0
> ;all other bits are not relevant and are initialized to 0
> movep #$037d00,x:M_TCR ;init trasmit control register
> movep #$037d00,x:M_TCR_1 ;init trasmit control register
> ;last slot interrupt disabled (bit23=0)
> ;transmit interrupt disabled (bit22=0)
> ;even slot interrupt disabled (bit21=0)
> ;exception interrupt enabled (bit20=1)
> ;transmitter normal operation (bit19=0)
> ;reserved (bit18=0)
> ;zero padding enabled (bit17=1)
> ;FS occurs 1 bit clock early (bit16=1)
> ;word length FS (bit15=0)
> ;32-bit slot length, 24-bit word length(bit14:10111)
> ;network mode (bit9:8)
> ;data left aligned (bit7=0)
> ;MSB shifted out first (bit6=0)
> ;all transmitters eabled except SDI0 (bit5:00000) (111110)
> movep #$17d00,x:M_RCR ;init receive control register
> movep #$17d00,x:M_RCR_1 ;init receive control register
> ; #$d07D01,x:M_RCR ;init receive control register
> ;last slot interrupt disnabled (bit23=0)
> ;receive interrupt disabled (bit22=0)
> ;even slot interrupt disabled (bit21=0)
> ;Receive exception interrupt enabled (bit20=1)
> ;receiver normal operation (bit19=0)
> ;reserved (bit18:17)
> ;the word length frame sync occurs 1 clk earlier with the first bit
> of the
> data first slot. (bit16=1)
> ;word length FS (bit15=0)
> ;32-bit slot length, 24-bit word length(bit14:10111)
> ;network mode (bit9:8)
> ;data left aligned (bit7=0)
> ;MSB shifted out first (bit6=0)
> ;reserved (bit5:4)
> ;receivers 3 and 2 disabled (bit3:2)
> ;receiver 1 disabled (bit1=0)
> ;receiver 0 disabled (bit0=0)
> ;When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled
> movep #$000fff,x:M_PCRC ;Enable ESAI port 111111011011
> movep #$000fff,x:M_PRRC
> movep #$00000,x:M_PCRE ;Enable ESAI_1 port 0000D8
> movep #$00000,x:M_PRRE
> ;reserved (bit23:120000000000)
> ;all pins enabled as ESAI ;???? except HCKT &
> HCKR(bit11:01111011011)
> movep #$000003,x:M_TSMA
> movep #$000003,x:M_TSMA_1
> ;#$000003,x:M_TSMA ;init transmit slot mask registers
> ;reserved (bit23:16000000)
> ;enable slots 15:0 (bit15:011111111111111)
> movep #$000000,x:M_TSMB
> movep #$000000,x:M_TSMB_1
> ; #$000003,x:M_TSMB
> ;reserved (bit23:16000000)
> ;enable slots 15:0 (bit15:011111111111111)
> movep #$000003,x:M_RSMA ;init receive slot mask registers
> movep #$000000,x:M_RSMA_1
> ;reserved (bit23:16000000)
> ;enable slots 15:0 (bit15:011111111111111)
> movep #$000000,x:M_RSMB
> movep #$000000,x:M_RSMB_1
> ;reserved (bit23:16000000)
> ;enable slots 15:0 (bit15:011111111111111)
> ;movep #$000000,x:M_TX0 ;zero out transmitter 0
> ;movep #$000000,x:M_TX1 ;zero out transmitter 1
> ;movep #$000000,x:M_TX2 ;zero out transmitter 2
> ;movep #$000000,x:M_TX3 ;zero out transmitter 3
> bset #0,x:M_RCR ;enable RX0
> andi #$FC,mr ;enable all interrupt levels
>
;**************************************************************************
> ; DMA
;**************************************************************************
> ;Common Registers
> movep #$1,x:M_DOR0
> movep #$fffffc,x:M_DOR1
> movep #$0,x:M_DOR2
> movep #$0,x:M_DOR3
>
> ;DMA0 Configuration for ESAI Receive Data RX0
> movep #$2e5ac0,x:M_DCR0
> ;DMA disable (bit23=0)
> ;DMA interrupt disable (bit22=0)
> ;word transfer mode, DE hold 1 after trasmission (bit21~191)
> ;DMA Priority Level 3 (highest) (bit18:17)
> ;NOT continuous transfer mode (bit16=0)
> ;DMA Request Source : ESAI Receive Data (RDF=1) (bit15~11011)
> ;No Three Dimensional mode (bit10=0)
> ;SourceAddress no update; DestinationAddress + 1
> ;Counter Mode A (bit9~41100)
> ;DMA Destination Memory Space X (bit3~2)
> ;DMA Source Memory Space X (bit1~0)
> movep #M_RX0,x:M_DSR0
> ;SourceAddress is #M_RX0 (#$FFFFA8)
> movep #$0,x:M_DDR0
> ;DestinationAddress is x:$000000
> movep #$3ff,x:M_DCO0 ; DCOf
> bset #13,x:M_IPRC ;enable DMA0 interrupt at priority level 1
> bset #22,x:M_DCR0 ;enable DMA0 interrupt
> bset #23,x:M_DCR0 ;enable DMA0
> bclr #9,SR ;enable interrupt priority levels 3,2,1
>
> ;DMA1 Configuration for ESAI Transmit Data SDO0~~SDO3 ,SDO6
> ;movep #$166080,x:M_DCR1
> ;DMA disable (bit23=0)
> ;DMA interrupt disable (bit22=0)
> ;;word transfer mode, DE hold 1 after trasmission (bit21~191)
> ;;block transfer mode, DE hold 1 after trasmission (bit21~190)
> ;row transfer mode, DE clear after trasmission (bit21~190)
> ;DMA Priority Level 3 (highest) (bit18:17)
> ;NOT continuous transfer mode (bit16=0)
> ;DMA Request Source : ESAI Transmit Data (TDE=1) (bit15~11100)
> ;No Three Dimensional mode (bit10=0)
> ;SourceAddress Gen Mode 2D according to Counter Mode B
> ;DestinationAddress
> (bit9~41000)
> ;DMA Destination Memory Space X (bit3~2)
> ;DMA Source Memory Space X (bit1~0)
> ;movep #$800,x:M_DSR1
> ;SourceAddress is #$800
> ;movep #M_TX4_1,x:M_DDR1
> ;DestinationAddress is x:M_TX0
> ;movep #$7ff004,x:M_DCO1 ; DMA1 Counter DCOf
> ;bset #15,x:M_IPRC ;enable DMA1 interrupt at priority level 1
> ;bset #22,x:M_DCR1 ;enable DMA1 interrupt
> ;bset #23,x:M_DCR1 ;enable DMA1
>
> ;bset #4,x:M_TCR_1 ;enable TX4_1
> ;bset #5,x:M_TCR_1 ;enable TX5_1
> ;bset #0,x:M_TCR ;enable TX0
> ;bset #1,x:M_TCR ;enable TX1
>
;**************************************************************************
> ; Main loop
;**************************************************************************
> mainloop
> movep a0,x:M_TX5_1
> bset #5,x:M_TCR_1
> nop
> nop
> ;jclr #15,x:M_SAISR_1,*
> inc a
> nop
> nop
> jmp mainloop
>
;**************************************************************************
> ; Subroutines
;**************************************************************************
>
> dma0int ; DMA0 interrupt routine
> bchg #0,r7
> jset #0,r7,rsw
> movep #0,x:M_DDR0 ;interrupt routine: prepare parameters
> move #$400,r0
> move #$1c00,r1
> dor #$400,rsw1
> move x:(r0)+,a0
> nop
> nop
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
>
> rsw1
> rti
> rsw
> movep #$400,x:M_DDR0 ;interrupt routine: prepare parameters
> move #0,r0
> move #$800,r1
> dor #$400,rsw2
> move x:(r0)+,a0
> nop
> nop
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
> move a0,x:(r1)+
> rsw2
> rti
> nop
> nop
> nop
>
> dma1int ; DMA1 interrupt routine
> movep #$800,x:M_DSR1 ;interrupt routine: prepare parameters
> bset #22,x:M_DCR1 ;enable DMA1 interrupt
> bset #23,x:M_DCR1 ;enable DMA1
> rti
> nop
> nop
> nop
>
> dma2int ; DMA2 interrupt routine
> movep #$800,x:M_DSR2 ;interrupt routine: prepare parameters
> rti
> nop
> nop
> nop
>
> org P:$0
> jmp START
>
> ;DMA0 Interrupt service Routine
> org p:I_DMA0
> jsr dma0int
>
> ;DMA1 Interrupt service Routine
> org p:I_DMA1
> jsr dma1int
>
> ;DMA2 Interrupt service Routine
> ; org p:I_DMA2
> ; jmp dma2int
>
> TRANSLATED TO CHINESE
>
> JTAGSP56367SAI˿ܺá
ESAI_1˿ڲòԣJTAGԵòSAI_1
> ظ !
> лл !
>
> Guo
> gybbh@gybb...
> עGռ䣡
> http://mail.sina.com.cn/chooseMode.html
>
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