genlock wrote:

>Hi
>
>As I was telling you before,
>
>When I manipulate the "sample" in the following way, I have the output
>changing from 0 dBFS to -6dBFS to -12dBFS:
>
>
>sample is 24 bit => 0 dBFS
>
>sample(23) & sample ( 23 downto 1) => -6dBFS
>
>Any ideas about what should be done to "sample" to make it go to -1dBFS
>instead?
>
>Thankyou
>
>  
>

Multiply by 10 ^ ( -1 /20)

Ren�

Hi

As I was telling you before,

When I manipulate the "sample" in the following way, I have the output
changing from 0 dBFS to -6dBFS to -12dBFS:


sample is 24 bit => 0 dBFS

sample(23) & sample ( 23 downto 1) => -6dBFS

Any ideas about what should be done to "sample" to make it go to -1dBFS
instead?

Thankyou

Hi Jerry and Randy

Thankyou for the info......

What I want to do is vary the audio amplitude from 0dBFS to -30 dBFS in
increments of 1 dB....

The audio amplitude is represented by a 24 bit binary value

This is the output of the FPGA

The input to the FPGA is the frequency information

Whats happening inside the FPGA is that the frequency is converted to
its amplitude

This amplitude value is given to a variable "sample" which is 24 bits

When sample is taken as the 24 bit output, its showing a value of 0dbFS

What manipulation should I do to this "sample" to make it change in
steps of 1?

thankyou

genlock wrote:
> Hi,
> 
> I am working on a project where the output is a 24 bit audio signal.
> I am using an FPGA chip to generate this audio signal.
> The input to the FPGA is a frequency value ( anywhere between 400hz to
> 10,000hz).
> Inside the FPGA, the frequency is converted to its amplitude by giving
> it to a sine look up table.
>  The output 'A'is then manipulated in such a way( dividing it by 2)
> that the amplitude increments by a constant value ( for eg: 6 dBFS)
> The output 'A' is manipulated and given out of the FPGA as a serial
> data ( 24 bits)
> This 24 bit audio ouptut seems to have the correct frequency
> information.
> 
> What I would like to know is..if this method is correct:that by
> dividing this output 'A' by a constant value 2, does it give a change
> of 6dBFS
> 
> If so, would dividing the 'A' by 1.122 give me a change of 1dBFS?
> 
> Or is there any other logic behind this?
> 
> Any kind of help would be highly appreciated.

You do know that a decibel is a ratio of logarithms of powers, and that 
if impedance is constant, power is the square of voltage, don't you? If 
you do your calculations with enough precision, you will find that 
successive divisions of the voltage by 2 actually change the level in dB 
by increments of 6.0206. Is that enough of a hint for your homework?

Jerry
-- 
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������

"genlock" <genlocks@gmail.com> writes:

> Hi,
> 
> I am working on a project where the output is a 24 bit audio signal.
> I am using an FPGA chip to generate this audio signal.
> The input to the FPGA is a frequency value ( anywhere between 400hz to
> 10,000hz).
> Inside the FPGA, the frequency is converted to its amplitude by giving
> it to a sine look up table.
>  The output 'A'is then manipulated in such a way( dividing it by 2)
> that the amplitude increments by a constant value ( for eg: 6 dBFS)
> The output 'A' is manipulated and given out of the FPGA as a serial
> data ( 24 bits)
> This 24 bit audio ouptut seems to have the correct frequency
> information.
> 
> What I would like to know is..if this method is correct:that by
> dividing this output 'A' by a constant value 2, does it give a change
> of 6dBFS
> 
> If so, would dividing the 'A' by 1.122 give me a change of 1dBFS?
> 
> Or is there any other logic behind this?
> 
> Any kind of help would be highly appreciated.

Hi,

You are essentially correct, but you're abusing the abbreviations. A
"change" in level is measured in dB, not dBFS. "dBFS" is an absolute
power level, while dB is relative. 

In general, the change C in dB between two power levels P1 and P2 is 

  C [dB] = 10 * log_10(P1/P2).

If we know the voltage levels V1 and V2, then

  C [dB] = 10 * log_10((V1^2 / R1) / (V2^2 / R2))
         = 10 * log_10(V1^2 / V2^2) + 10 * log_10(R2 / R1).

If we assume R2 = R1, then R2/R1 = 1 and the second term goes to zero,
so that

  C [dB] = 20 * log_10(V1 / V2).

-- 
Randy Yates
Sony Ericsson Mobile Communications
Research Triangle Park, NC, USA
randy.yates@sonyericsson.com, 919-472-1124

Hi,

I am working on a project where the output is a 24 bit audio signal.
I am using an FPGA chip to generate this audio signal.
The input to the FPGA is a frequency value ( anywhere between 400hz to
10,000hz).
Inside the FPGA, the frequency is converted to its amplitude by giving
it to a sine look up table.
 The output 'A'is then manipulated in such a way( dividing it by 2)
that the amplitude increments by a constant value ( for eg: 6 dBFS)
The output 'A' is manipulated and given out of the FPGA as a serial
data ( 24 bits)
This 24 bit audio ouptut seems to have the correct frequency
information.

What I would like to know is..if this method is correct:that by
dividing this output 'A' by a constant value 2, does it give a change
of 6dBFS

If so, would dividing the 'A' by 1.122 give me a change of 1dBFS?

Or is there any other logic behind this?

Any kind of help would be highly appreciated.

Thankyou