On Thursday, April 12, 2018 at 8:46:06 PM UTC-7, Steve Pope wrote:
>
> I'm not quite sure what you're saying here, however in a CIC filter
> as standardly implemented in 2's complement, there should be no rounding.
> There should only be truncation, and when truncating, a value should
> never become more positive. The lower bits should be discarded without
> further rounding. So it's always "truncation towards negative infinity".
>
> So, what you just wrote above sounds very suspicious.
>
>
> Steve
Hi Steve,
Thank you very much for the reply. Indeed my original post is a very confusing and suspicious one, and I apologize for that. Let me try again here.
I am trying to design a decimation filter with decimation rate at 100 and bandwidth around 1Hz to 100Hz. Of course the exact bandwidth will be finalized by the following Low Pass and High Pass filters, but that's not the focus here. The required input bit (Bin) is 1 and the output bit (Bout) is 16.
Currently I have two cascade stages of CIC decimation filter to achieve this goal. The first stage of CIC filter has decimation rate at 5, with 2 integrators and 2 differentiators. Bin=1. Rdec1=6. Based on Hogenauer's paper, the bit widths for the 2 integrators are Rint1=[6 6], and the bit widths for the 2 differentiators are Rdif1=[6 6].
The second stage of CIC filter has decimation rate at 20, with 3 integrators and 3 differentiators. Bin=6. Bout=16. The bit widths for the 3 integrators are Rint2=[19 19 19], and the bit widths for the 3 differentiators are Rdif2=[19 19 18].
So the matlab code looks like this:
F0 = 5; %Input Sine wave frequency
FS = 50e3; % Initial Sample Rate
Rint1 = [6 6]; % Vector of register lengths for 1st stage integrators
Rdif1 = [6 6]; % Vector of register lengths for 1st stage differentiators
M1 = [1 1]; % Differential delay of differentiators
Rdec1 = 6; % bit width of output of dec1
Rint2 = [19 19 19]; % Vector of register lengths for 2nd stage integrators
Rdif2 = [19 19 18]; % Vector of register lengths for 2nd stage differentiators
M2 = [1 1 1]; % Differential delay of differentiators
Rdec2 = 16; % bit width of output of dec2
OSR = [5 20] ; %Oversampling rate for each decimation stage
[x sd] = sd_mod(FS, 1e-3, F0, T); %sd_mod() is a first order sigma-delta modulator with a sinewave input
% Decimation Stage 1
% 2 cascades
int1_1 = integrator(FS, Rint1(1), sd);
int1_2 = integrator(FS, Rint1(2), int1_1);
% Decimation
d1 = downsample(int1_2, OSR(1), 0);
dif1_1 = comb(FS/OSR(1), Rdif1(1), M1(1), d1); % comb Function definition: y=comb(FS, nbits, M, x)
dif1_2 = comb(FS/OSR(1), Rdif1(1), M1(2), dif1_1);
dec1 = dif1_2;
%Decimation Stage 2
% 3 cascades
int2_1 = integrator(FS/OSR(1), Rint2(1), dec1);
int2_2 = integrator(FS/OSR(1), Rint2(2), int2_1);
int2_3 = integrator(FS/OSR(1), Rint2(3), int2_2);
% Decimation
d2 = downsample(int2_3, OSR(2), 0);
dif2_1 = comb(FS/prod(OSR(1:2)), Rdif2(1), M2(1), truncate(d2,Rint2(3)-Rdif2(1)));
dif2_2 = comb(FS/prod(OSR(1:2)), Rdif2(2), M2(2), truncate(dif2_1,Rdif2(1)-Rdif2(2)));
dif2_3 = comb(FS/prod(OSR(1:2)), Rdif2(3), M2(3), truncate(dif2_2,Rdif2(2)-Rdif2(3)));
dec2 = truncate(dif2_3,Rdif2(3)-Rdec2);
At each differentiator, the lower bits are truncated.
Function comb() goes like this:
function y = comb(FS, nbits, M, x)
y(1:M) = x(1) * ones(1,M);
for i = M+1:(length(x))
y(i) = x(i) - x(i-M);
y(i) = modulo(y(i), nbits);
end
Function x=modulo(x,nbits)
R = 2^nbits;
delta = 1; %quantization step
x=fix(x); %ensures only integers
nmax = R;
max_x = nmax-delta;
min_x = 0;
for i=1:length(x)
while x(i) > max_x
x(i) = x(i)- nmax;
end
while x(i) < min_x
x(i) = x(i)-(-nmax);
end
end
Here is the problem I have.
From lower-bits-truncated dif2_2 (refer to d22 here) to dif2_3 (refer to d23), at index 101,
d22(101)=61164, d22(102)=8127
so d23(102)= d22(102)-d22(101)=-53037
in 2's complement, through function modulo, the real output of d23 will be
-53037 + 2^16 = 12499
At index 103, d22(103) = 20628
so d23(103) = d22(103) - d22(102) = 12501
At index 104, d23(104) ends up with the same range of value around 12500.
So in this cycle of sinewave output, there are three points of almost flat line. The happens to every half cycle of the sinewave. Because the decimation filter gain is at 25000. After offset shifting, this looks like a zero-crossing distortion at each cycle.
Obviously in the real system, the input wave wouldn't be a perfect sinewave, and we rely on the hardware to detect all the waves with frequency in the passband and make decisions. I am concerned that this distortion will cause confusion in the system downstream.
Any suggestions or comments?