At first I thought you were simply noticing the intentional use of the
upper address lines to select the memory in 16+16, 16+0, 0-16, or 0-0
sections (floating point on the VC33 works just fine using only the
upper 16 bits)... but then I saw the data bits flipped in the SRAM, and
then in the FeRAM.
Yep the (upper) SRAM data bits are scrambled and quite a bit is flipped
around in the FeRAM. Not that this matters much to the DSP or the
memory(s). As long as all of the bits get turned on and off at the
right time neither the DSP or the memories will care. For example, the
DSP only sees the SRAM in 16 bit chunks and the FeRAM in 8 bit chunks.
My bet is that board layout guy used this to fit the routing into fewer
Incidentally, YOU CANT DO THIS WITH A TYPICAL FLASH. The FeRAM is quite
different in that it truly is random access read or write. On the other
hand, FLASH needs to be erased and written in sectors with very specific
algorithms and timings. Basically a major pain in the ass. If you can
afford to use an FeRAM or an MRAM (recently in the news for FreeScale
and Ramtron) it is far easier to use and has no wear out mechanism like
FLASH. Very good devices for data logging and things like buffering the
data into a hard disk should its power supply begin to fail (if a power
fail is detected you could keep the data in FeRAM/MRAM rather than
risking a write to disk)
BTW, Both Ramtron and Freescale have or are working on larger 4 Mb (and
larger) arrays. Also, if you want to read up on MRAM, NVE Corporation
has been supplying some of that IP. They also make some rather
interesting sensors and couplers. I dont have any affiliation with these
companies, but I do like to keep tabs on them as either technology looks
very promising to me.
As far as the order for bringing up the supplies, the minimum
requirement is to make sure the core supply does not exceed the IO
supply (else risk a latchup, so use a diode), and it probably is not
advisable to let the IO supply widely exceed the core supply (a couple
more diodes). My personal preference is to let the core up at the same
time or slightly ahead of the periphery. I say this because the core
will actually function (at a much reduced clock rate) with a 1V supply.
This can help since the core which is connected to the IO periphery is
in control of the periphery signals (that is, the IO powers up in a more
or less defined state)!
Hope this helps
DSP and Analog Consultant
Lincoln, Ma 01773
rasit gokalan wrote:
Hello , I have TMS320VC33 DSK . In the DSK schematic ,some of the the
adress and data lines do not match to adress and data pins of the SRAM
and FeRAM memory.Is there any someone having any idea for this connection.