In case anyone is interested, I did end up finding something related to
speeding up the viterbi decoder.  It in not quite what I was expecting,
but seems promissing.  The reference is the following:

"High-Speed Parallel Viterbi Decoding: Algorithm and
VLSI-Architecture", G. Fettweis and H. Meyr, IEEE Communication
Magazine, May 1991.

BR,
Phil

What I am trying to do is increase the throughput of a viterbi decoder
that is currently contrained by the FPGA clock rate.

What you say is right.  The decoder would have to operate on symbols
rathter than on bits.  I may have been incorrect to assume that this
was tied to the use of radix 2 butterflies in the trellis.

Do you know of any papers to do with the symbol decoders to solve my
bottleneck?

Data rate higher than clock rate => the viterbi decoder operates on
symbols, rather than on bits. You need some kind of TCM decoder? But
what has that got to do anything with butterflies and radix 2?

What exactly are you going to decode with your Viterbi decoder?

Hi,

I'm looking for any good references for viterbi implementations that
allow for a data rate higher than the clock rate.

As I understand it, this implies using butterflies in the trellis of
higher than radix 2.

Any help is much appreciated.

Phil