At 09:46 AM 12/8/99 -0500, you wrote: > If we use this convenient scaling for coefficients, we need one left shift >after multiply to make it work. Consider a signal of 2, multiplied by a >coefficient of 1/2 (4000 Hex). My hex calculator does 2 * 4000 = 8000. If I >take the high 16 bits, I get zero. Instead, the 2181 does 2 * 4000 = 8000 and >then does one left shift yielding 10000 Hex. If I take just the high 16 bits I >get the desired product of 1. To obtain this fractional multiply clear bit 4 in >the MSTAT register with the DIS MMODE instruction. Thanks for the explanation David. It is now clear in my mind what 1.15 integer multiplication involves (including the redundent sign bit). Can anyone else confirm that the ADSP-2181 Simulator from AD has problems with INTEGER (16.0) multiplication? Either I havn't been using MSTAT properly or the simulator has a bug (Al does suggest it might have a few). Regards, Luke

OK, Let me try a simple explanation of integer and fractional multiplication. Integer multiplies are what we learn in school, 2 * 2 = 4, 16 * 16 = 256 and so on. For lots of things, calculating array addresses, or the size of a two dimensional array or the number of fenceposts required to do 1500 feet of fence, or .... , you want integer multiplication. In the 2181 you get integer multiplies by setting bit 4 in the MSTAT register. Use the "ENA MSTAT" instruction to obtain integer multiplies. Fractional multiplies are a little more confusing. When we multiply two 16 bit numbers together, we obtain 32 bits of product. The multiplier supports this by providing a 32 bit product register (Mr1 and Mr0). For this discussion, ignore the 40 bit part and the mx register. If the first multiply gives a 32 bit product, and we keep all 32 bits, then the second multiply will be 32 bits * 32 bits yielding a 64 bit product, and the third multiply is worse, and we are on the road to disaster. Nobody does that. What everyone does, is multiply 16 bits * 16 bits and keep ONLY 16 bits of the 32 bit product. This way the number doesn't grow and strangle the DSP. If we keep the HI 16 bits of the 32 bit product, this amounts to an integer multiplication followed by a 16 bit right shift which is equivalent to divide by 2**16. This tends to make the number shrink. For instance, 1 * anything = 0, 2 * anything = anything / 2**15, 4 * anything = anything/ 2**14 and so. A convenient way to think about this is to call the coefficient a binary fraction. Place the binary point one bit in from the MSB (16.15). Then 4000 Hex = 1/2, 2000 hex = 1/4 and 7FFF hex is almost but not quite +1. 8000 Hex is -1. This scaling gives full 16 bit precision to the coefficients, which is desirable to reduce quantization noise in digital filters. If we use this convenient scaling for coefficients, we need one left shift after multiply to make it work. Consider a signal of 2, multiplied by a coefficient of 1/2 (4000 Hex). My hex calculator does 2 * 4000 = 8000. If I take the high 16 bits, I get zero. Instead, the 2181 does 2 * 4000 = 8000 and then does one left shift yielding 10000 Hex. If I take just the high 16 bits I get the desired product of 1. To obtain this fractional multiply clear bit 4 in the MSTAT register with the DIS MMODE instruction. David J. Starr Senior Systems Video Engineer Computer Products Division 781 937 1518 HTTP://www.analog.com/industry/video > ---------- > From: Luke Enriquez[SMTP:] > Reply To: > Sent: Tuesday, 07 December, 1999 7:40 PM > To: > Subject: [adsp] Re: Integer multiplication and ADSP-2181 > > Hi, > > Can some explain to me why the integer multiplication leaves > the result shifted one bit to the left. > > if mx0 = 10h and my0 = 10h then > > ie mr = mx0 * my0 (ss) > > leaves mr = 200h when it should be 100h. > > There is mention of 1.15 format and 16.0 format with respect to > MSTAT (I think) but even changing this bit doesn't change the > result. I presume the reason is to give you a fast multiplier that > only takes one clock cycle, and you shift it right if you need to > or half the magnitude of your FIR co-efficients, etc.... > > Any ideas are appreciated. > > Regards, > Luke > > ------------------------------- > Luke Enriquez (VK3EM) Trio Communications 2000 Pty. > Ltd. > Electronics Design Engineer. 41 Aster Ave. > B.Eng (Comms) Hon. Carrum Downs, Victoria. 3201 > 03-9775-0505 (BH) Australia > 0414-679-432 (Mob) http://www.trio.com.au > > In the market for computer hardware or software? Compare prices on > more that 100,000 products at CNET.com. Get all the latest news, > reviews and prices! http://clickhere.egroups.com/click/1611 > -- Create a poll/survey for your group! > -- http://www.egroups.com/vote?listnamesp&m=1

At 03:52 PM 12/8/99 +1100, you wrote: >At 09:57 PM 12/7/99 -0600, you wrote: > >>The reason for the shift is that normally fixed point processors assume >>1.15 math. This means that all values are between 1(almost) and -1. >>If you do not shift, the result has a redundant sign bit (2.30 format). The >>shift leaves the result in 1.31 format. > >Granted, but the ADSP-2181 simulator shows the shift occuring even when >the MSTAT register is set to 16.0 maths. I would have thought that if you >told the 2181 via MSTAT that you were operating in 16.0 format, it would >not shift unless is has to due to execution speed constraints. It could be >a bug in the simulator too. I do remember reading somewhere in the >family manual that the result should be left un-shifted if your >operating in 16.0 mode. >Thanks for your comments. > >Regards, >Luke > >------------------------------- >Luke Enriquez (VK3EM) Trio Communications 2000 Pty. Ltd. >Electronics Design Engineer. 41 Aster Ave. >B.Eng (Comms) Hon. Carrum Downs, Victoria. 3201 >03-9775-0505 (BH) Australia >0414-679-432 (Mob) http://www.trio.com.au If you set bit 4 of MSTAT, Integer Mode , the result will not shift ever. If you use integer mode, I would suggest resetting MSTAT back to fractional mode right away. Integer mode is the exception for most signal processing. Maybe the simulator is at fault. The ADI tools are far from perfect. I have used both modes sucessfully. Al Clark

At 09:57 PM 12/7/99 -0600, you wrote: >The reason for the shift is that normally fixed point processors assume >1.15 math. This means that all values are between 1(almost) and -1. >If you do not shift, the result has a redundant sign bit (2.30 format). The >shift leaves the result in 1.31 format. Granted, but the ADSP-2181 simulator shows the shift occuring even when the MSTAT register is set to 16.0 maths. I would have thought that if you told the 2181 via MSTAT that you were operating in 16.0 format, it would not shift unless is has to due to execution speed constraints. It could be a bug in the simulator too. I do remember reading somewhere in the family manual that the result should be left un-shifted if your operating in 16.0 mode. Thanks for your comments. Regards, Luke ------------------------------- Luke Enriquez (VK3EM) Trio Communications 2000 Pty. Ltd. Electronics Design Engineer. 41 Aster Ave. B.Eng (Comms) Hon. Carrum Downs, Victoria. 3201 03-9775-0505 (BH) Australia 0414-679-432 (Mob) http://www.trio.com.au

At 11:40 AM 12/8/99 +1100, you wrote: >Hi, > >Can some explain to me why the integer multiplication leaves >the result shifted one bit to the left. > >if mx0 = 10h and my0 = 10h then > >ie mr = mx0 * my0 (ss) > >leaves mr = 200h when it should be 100h. > >There is mention of 1.15 format and 16.0 format with respect to >MSTAT (I think) but even changing this bit doesn't change the >result. I presume the reason is to give you a fast multiplier that >only takes one clock cycle, and you shift it right if you need to >or half the magnitude of your FIR co-efficients, etc.... > >Any ideas are appreciated. > >Regards, >Luke > >------------------------------- >Luke Enriquez (VK3EM) Trio Communications 2000 Pty. Ltd. >Electronics Design Engineer. 41 Aster Ave. >B.Eng (Comms) Hon. Carrum Downs, Victoria. 3201 >03-9775-0505 (BH) Australia >0414-679-432 (Mob) http://www.trio.com.au > >In the market for computer hardware or software? Compare prices on >more that 100,000 products at CNET.com. Get all the latest news, >reviews and prices! http://clickhere.egroups.com/click/1611 >-- Create a poll/survey for your group! >-- http://www.egroups.com/vote?listnamesp&m=1 The reason for the shift is that normally fixed point processors assume 1.15 math. This means that all values are between 1(almost) and -1. If you do not shift, the result has a redundant sign bit (2.30 format). The shift leaves the result in 1.31 format. Al Clark