On Tue, 12 Dec 2006, rk_stevean wrote:
> Hi
>
> I am workin gon the customised board with ADSp 21160 and 25 MHz
> crystal on it.
> I am having problem in booting at higher frequency ie, at 100 Mhz(4:1
> Clk cfg).
>
> At 2:1 the boot code is working fine.
>
> There is a slight variation in the boot code that is getting copied at
> the location in 3:1 clk cfg.
>
> Consider this part of code that is getting copied at 2:1 in the
> mentioned location
>
> 0x4006A dm(0x41)=m13;
> 0x4006B dm(0x46)=m14;
> 0x4006C i15=0x40004;
> 0x4006D call 0x400ea;
>
> Now, at 3:1 clk cfg on boot the following code is getting written in
> the same location as
>
> 0x4006A dm(0x41)=m13;
> 0x4006B dm(0x46)=m14;
> 0x4006C i15=0x40004;
> 0x4006D jump 0x4006a;
> The instruction at 0x4006D is jumping back to 0x4006A and this is
> executing infinitely. Thus the application code not getting written.
>
> What might be the problem? Why is the instruction at 0x4006d changing
> from call to jump at 3:1 clk cfg?
I'm betting it's the speed of your boot flash. First copy every
thing
from flash at 25MHz, then turn on the PLL. If you have to copy code after
that, put enough wait states into the bus to slow the transfer down so you
meet the timing constraints on the flash.
Patience, persistence, truth,
Dr. mike