Reply by steh...@hotmail.com March 9, 20072007-03-09
Hi Again,
I have again done some analysis and found that the base address being loaded into the I2 register is incorrect. I dont know why. This is what the debugger shows, I2(12 right after the instruction I2=_SPORT0_Tx_Buffer_1; The watch window shows that &_SPORT0_Tx_Buffer_1[0]=0x2800. The break point is right after the I2 assignment instruction. Can any one tell me what is happening here????

Thanks and Regards,
Saba

Hi,
>First of all I am sorry if you are receiving multiple copies of this mail.
>
>I am trying to program and communicate with CODEC AD73311AR on SPORT0. I have programmed the CODEC to work at 1.024MHz SClock and 32KHZ sampling frequency. I am using I2 and I3 for initializing SPORT0. I am attaching the code for CODEC and SPORTs initialization function. It is clear from the code that I have buffers for SPORT0 Tx and SPORT0 Rx autobuffering initialized. If I run this code on EZ kit, the address in I2 register should be equal to the base address of SPORT1 TX buffer when SPORT0 Tx interrupt is called, but it is pointing to 18 addresses advanced.
>
>If I change the code such that the ADSP-218x is generating the serial clock of 1.024MHz and run it in the simulation mode it runs fine. I cannot understand why the interrupt is being called after extra samples have been recieved in EZ kit environment. I am attaching the code for reference. I hope this time I am able to make myself clear.
>
>_CodecInit:
> leaf_entry;
> dm(save_dmovlay)=dmovlay;
> //reset codec
> reset fl0;
> //Disable SPORTS
> ay0 = 0;
> dm (System_Control_Reg) = ay0;
>
> //clear pending interrupts
> ifc = b#0000000011111111;
> nop;
> // Configure Sport0
>
> //ay0=b#0110101000001111;
> ay0 = b#0010100000001111; //Frame Sync Loopback
> // |||||||||||||||+------- SLEN 0 (Serial Word length - 1)
> // ||||||||||||||+-------- SLEN 1
> // |||||||||||||+--------- SLEN 2
> // ||||||||||||+---------- SLEN 3
> // |||||||||||+----------- DTYPE 0 (Data Format) 00=right justify, zero-fill unused MSBs 01=right justify, sign-extend into unused MSBs
> // ||||||||||+------------ DTYPE 1
> // |||||||||+------------- INVRFS (Invert Rx Frame Sync)
> // ||||||||+-------------- INVTFS (Invert Tx Frame Sync)
> // |||||||+--------------- IRFS (Internal RFS enable)
> // ||||||+---------------- ITFS (Internal TFS enable)
> // |||||+----------------- TFSW (Tx Frame Sync Width) 0 = Normal Framing(default) 1 = Alternate Framing
> // ||||+------------------ TFSR (Tx Frame Sync Required)
> // |||+------------------- RFSW (Rx FSW)
> // ||+-------------------- RFSR (Receive FS Reqd)
> // |+--------------------- ISCLK(0=external(default), 1=internal)
> // +---------------------- MCE (Mutl-ch Enable)
> dm(SPORT0_Control_Reg) = ay0;
> ay0 = 34;
> dm(SPORT0_SCLKDIV) = ay0;
> AX0=0;
> I2=_SPORT0_Tx_Buffer_0;
> L2=length(_SPORT0_Tx_Buffer_0);
> dm(_SPORT0_Tx_which_Buffer)=AX0;
>
> //Rx uses I1 and M0
> I3=_SPORT0_Rx_Buffer_0;
> L3=length(_SPORT0_Rx_Buffer_0);
> dm(_SPORT0_Rx_which_Buffer)=AX0;
>
> // Enable Auto-Buffering
> ay0 = b#0000010010110111;
> //ay0 = b#0000101101111011;
> // | | ||
> // | | ||+-------RX autobuffering 1=enabled 0=disabled
> // | | |+--------TX autobuffering 1=enabled 0=disabled
> // | +-------------------Biased Rounding 1=enabled 0=disabled
> // +---------------------Clock Out
> dm(SPORT0_Autobuf) = ay0;
>
> //Configure Sport1
>
> ay0 = b#0110101100000111; //Non Frame Sync Loopback
> // |||||||||||||||+------- SLEN 0 (Serial Word length - 1)
> // ||||||||||||||+-------- SLEN 1
> // |||||||||||||+--------- SLEN 2
> // ||||||||||||+---------- SLEN 3
> // |||||||||||+----------- DTYPE 0 (Data Format) 00=right justify, zero-fill unused MSBs 01=right justify, sign-extend into unused MSBs
> // ||||||||||+------------ DTYPE 1
> // |||||||||+------------- INVRFS (Invert Rx Frame Sync)
> // ||||||||+-------------- INVTFS (Invert Tx Frame Sync)
> // |||||||+--------------- IRFS (Internal RFS enable)
> // ||||||+---------------- ITFS (Internal TFS enable)
> // |||||+----------------- TFSW (Tx Frame Sync Width) 0 = Normal Framing(default) 1 = Alternate Framing
> // ||||+------------------ TFSR (Tx Frame Sync Required) 0 = External 1 = Internal
> // |||+------------------- RFSW (Rx FSW)
> // ||+-------------------- RFSR (Receive FS Reqd)
> // |+--------------------- ISCLK(0=external(default), 1=internal)
> // +---------------------- MCE (Mutl-ch Enable)
> dm(SPORT1_Control_Reg) = ay0;
> // Dis-able Auto-Buffering
> ay0 = b#1000000000000000;
> // |||| ||
> // |||| |+-------RX autobuffering 1=enabled 0=disabled
> // |||| +--------TX autobuffering 1=enabled 0=disabled
> // |||+-------------------Context Clear 1=Soft reset 0=resume
> // ||+--------------------Force Power Down 1=Force
> // |+---------------------Delay after power up 1ay
> // +----------------------Xtal Disable duting power down
> dm(SPORT1_Autobuf) = ay0;
> //Set Sport1 Serial Clock
> ay0 = UARTCLK;
> dm(SPORT1_SCLKDIV) = ay0;
> AY0=0x10;
> dm(SPORT1_RFSDIV)=AY0;
>
> //Enable SPORTS
> ay0 = b#0001000000000111;//enable SPORT0 (bit 12) */
>
> dm (System_Control_Reg) = ay0;
>
> //disable interrupt nesting & make it Edge Sensitive
> icntl = 0x07;
> //setup timers
> ax0;
> dm(TSCALE)=ax0;
> ax0001;
> dm(TCOUNT)=ax0;
> dm(TPERIOD)=ax0;
>
> //enable interrupts(0 = disable , 1 = enable )
> imask = b#0001100111;
> // |||||||||+-- timer
> // ||||||||+--- SPORT1 Rx or IRQ0
> // |||||||+---- SPORT1 Tx or IRQ1
> // ||||||+----- BDMA
> // |||||+------ IRQE
> // ||||+------- SPORT0 Rx
> // |||+-------- SPORT0 Tx
> // ||+--------- IRQL0
> // |+---------- IRQL1
> // +----------- IRQ2
> //Put first word in tx0 and increment command count
> dmovlay=0;
> AX0=DM(I2,M1);
> TX0=AX0;
>
> dm(saved_i0)=I0;
> dm(saved_m0)=M0;
> M0=0;
> I0=_SPORT1_Tx_Buffer_0;
> AX0=dm(I0,M1);
> TX1=AX0;
> dm(_SPORT1_Tx_Curr_Buff_Base)=I0;
> I0=_SPORT1_Rx_Buffer_0;
> dm(_SPORT1_Rx_Curr_Buff_Base)=I0;
>
> dm(_SPORT1_Tx_which_Buffer)=M0;
> dm(_SPORT1_Rx_which_Buffer)=M0;
> dm(_SPORT1_Rx_Curr_Index)=M0;
> M0=1;
> dm(_SPORT1_Tx_Curr_Index)=M0;
> I0=dm(saved_i0);
> M0=dm(saved_m0);
> ////////////////
> // bring codec out of reset
> dmovlay=dm(save_dmovlay);
>
> set fl0;
>leaf_exit;
>_CodecInit.end:
>
>Thanks and Regards,
>
>Saba
Reply by steh...@hotmail.com March 8, 20072007-03-08
Hi,
First of all I am sorry if you are receiving multiple copies of this mail.

I am trying to program and communicate with CODEC AD73311AR on SPORT0. I have programmed the CODEC to work at 1.024MHz SClock and 32KHZ sampling frequency. I am using I2 and I3 for initializing SPORT0. I am attaching the code for CODEC and SPORTs initialization function. It is clear from the code that I have buffers for SPORT0 Tx and SPORT0 Rx autobuffering initialized. If I run this code on EZ kit, the address in I2 register should be equal to the base address of SPORT1 TX buffer when SPORT0 Tx interrupt is called, but it is pointing to 18 addresses advanced.

If I change the code such that the ADSP-218x is generating the serial clock of 1.024MHz and run it in the simulation mode it runs fine. I cannot understand why the interrupt is being called after extra samples have been recieved in EZ kit environment. I am attaching the code for reference. I hope this time I am able to make myself clear.

_CodecInit:
leaf_entry;
dm(save_dmovlay)=dmovlay;
//reset codec
reset fl0;
//Disable SPORTS
ay0 = 0;
dm (System_Control_Reg) = ay0;

//clear pending interrupts
ifc = b#0000000011111111;
nop;
// Configure Sport0

//ay0=b#0110101000001111;
ay0 = b#0010100000001111; //Frame Sync Loopback
// |||||||||||||||+------- SLEN 0 (Serial Word length - 1)
// ||||||||||||||+-------- SLEN 1
// |||||||||||||+--------- SLEN 2
// ||||||||||||+---------- SLEN 3
// |||||||||||+----------- DTYPE 0 (Data Format) 00=right justify, zero-fill unused MSBs 01=right justify, sign-extend into unused MSBs
// ||||||||||+------------ DTYPE 1
// |||||||||+------------- INVRFS (Invert Rx Frame Sync)
// ||||||||+-------------- INVTFS (Invert Tx Frame Sync)
// |||||||+--------------- IRFS (Internal RFS enable)
// ||||||+---------------- ITFS (Internal TFS enable)
// |||||+----------------- TFSW (Tx Frame Sync Width) 0 = Normal Framing(default) 1 = Alternate Framing
// ||||+------------------ TFSR (Tx Frame Sync Required)
// |||+------------------- RFSW (Rx FSW)
// ||+-------------------- RFSR (Receive FS Reqd)
// |+--------------------- ISCLK(0=external(default), 1=internal)
// +---------------------- MCE (Mutl-ch Enable)
dm(SPORT0_Control_Reg) = ay0;
ay0 = 34;
dm(SPORT0_SCLKDIV) = ay0;
AX0=0;
I2=_SPORT0_Tx_Buffer_0;
L2=length(_SPORT0_Tx_Buffer_0);
dm(_SPORT0_Tx_which_Buffer)=AX0;

//Rx uses I1 and M0
I3=_SPORT0_Rx_Buffer_0;
L3=length(_SPORT0_Rx_Buffer_0);
dm(_SPORT0_Rx_which_Buffer)=AX0;

// Enable Auto-Buffering
ay0 = b#0000010010110111;
//ay0 = b#0000101101111011;
// | | ||
// | | ||+-------RX autobuffering 1=enabled 0=disabled
// | | |+--------TX autobuffering 1=enabled 0=disabled
// | +-------------------Biased Rounding 1=enabled 0=disabled
// +---------------------Clock Out
dm(SPORT0_Autobuf) = ay0;

//Configure Sport1

ay0 = b#0110101100000111; //Non Frame Sync Loopback
// |||||||||||||||+------- SLEN 0 (Serial Word length - 1)
// ||||||||||||||+-------- SLEN 1
// |||||||||||||+--------- SLEN 2
// ||||||||||||+---------- SLEN 3
// |||||||||||+----------- DTYPE 0 (Data Format) 00=right justify, zero-fill unused MSBs 01=right justify, sign-extend into unused MSBs
// ||||||||||+------------ DTYPE 1
// |||||||||+------------- INVRFS (Invert Rx Frame Sync)
// ||||||||+-------------- INVTFS (Invert Tx Frame Sync)
// |||||||+--------------- IRFS (Internal RFS enable)
// ||||||+---------------- ITFS (Internal TFS enable)
// |||||+----------------- TFSW (Tx Frame Sync Width) 0 = Normal Framing(default) 1 = Alternate Framing
// ||||+------------------ TFSR (Tx Frame Sync Required) 0 = External 1 = Internal
// |||+------------------- RFSW (Rx FSW)
// ||+-------------------- RFSR (Receive FS Reqd)
// |+--------------------- ISCLK(0=external(default), 1=internal)
// +---------------------- MCE (Mutl-ch Enable)
dm(SPORT1_Control_Reg) = ay0;
// Dis-able Auto-Buffering
ay0 = b#1000000000000000;
// |||| ||
// |||| |+-------RX autobuffering 1=enabled 0=disabled
// |||| +--------TX autobuffering 1=enabled 0=disabled
// |||+-------------------Context Clear 1=Soft reset 0=resume
// ||+--------------------Force Power Down 1=Force
// |+---------------------Delay after power up 1ay
// +----------------------Xtal Disable duting power down
dm(SPORT1_Autobuf) = ay0;
//Set Sport1 Serial Clock
ay0 = UARTCLK;
dm(SPORT1_SCLKDIV) = ay0;
AY0=0x10;
dm(SPORT1_RFSDIV)=AY0;

//Enable SPORTS
ay0 = b#0001000000000111;//enable SPORT0 (bit 12) */

dm (System_Control_Reg) = ay0;

//disable interrupt nesting & make it Edge Sensitive
icntl = 0x07;
//setup timers
ax0;
dm(TSCALE)=ax0;
ax0001;
dm(TCOUNT)=ax0;
dm(TPERIOD)=ax0;

//enable interrupts(0 = disable , 1 = enable )
imask = b#0001100111;
// |||||||||+-- timer
// ||||||||+--- SPORT1 Rx or IRQ0
// |||||||+---- SPORT1 Tx or IRQ1
// ||||||+----- BDMA
// |||||+------ IRQE
// ||||+------- SPORT0 Rx
// |||+-------- SPORT0 Tx
// ||+--------- IRQL0
// |+---------- IRQL1
// +----------- IRQ2
//Put first word in tx0 and increment command count
dmovlay=0;
AX0=DM(I2,M1);
TX0=AX0;

dm(saved_i0)=I0;
dm(saved_m0)=M0;
M0=0;
I0=_SPORT1_Tx_Buffer_0;
AX0=dm(I0,M1);
TX1=AX0;
dm(_SPORT1_Tx_Curr_Buff_Base)=I0;
I0=_SPORT1_Rx_Buffer_0;
dm(_SPORT1_Rx_Curr_Buff_Base)=I0;

dm(_SPORT1_Tx_which_Buffer)=M0;
dm(_SPORT1_Rx_which_Buffer)=M0;
dm(_SPORT1_Rx_Curr_Index)=M0;
M0=1;
dm(_SPORT1_Tx_Curr_Index)=M0;
I0=dm(saved_i0);
M0=dm(saved_m0);
////////////////
// bring codec out of reset
dmovlay=dm(save_dmovlay);

set fl0;
leaf_exit;
_CodecInit.end:

Thanks and Regards,

Saba