Apologies. Looks like I ranted without reading all your well framed
answers to Randy's query. 

--Bhooshan

Hi Randy--

>> Would you rather service an interrupt every sample, or every 16
samples?
>
>Um, yes, true. I guess I'm not used to bit-banging like this since the
>early 80's. So the choice is between M*F MIPS or F MIPS, 

Excuse my wretched sense for profanity and puns: your abbrievations _do_
have apt equivalent expansion in the land of technical frustrations! :-)


>where
>F is the sample rate and M is some integer representing the
>interrupt overhead. 

Ofcourse, you wouldnt say it!

--Bhooshan




Yeah, sure I'd choose F MIPS, but that's still
>horrible! 
>
>--RY
>
>

Hi Randy--


>Hi Tim,
>
>I scanned the documents quickly, but I think you're correct. There are
>16 registers that can be used like a FIFO. However, so what? As you
>say, it still takes 1 clock per sample to transfer them to RAM, so
>whether you take 16 clocks every 16/Fs, or 1 clock every 1/Fs,
>what's the difference?
>
>At your rates it's not a problem. But we're planning on running this
>at up to 5.12 MHz in simultaneous capture mode, so we'd be shoving
>10+ MIPS down the toilet.
>
>I feel like kicking TI's butt for not putting a DMA controller on this
>machine.
>
>--RY

Though am no expert on C2812, my own understanding on this architecture is
that it is optimized for control algorithms.And that control algorithms
normally have _very_ low tolerance for output latency and hence would
necessitate sample-by-samply processing to mitigate this. This
sample-by-sample techniques, maintains the necessary in-to-out time demand
placed by control algorithms. So, 2812 is _best_ used in sample-by-sample
processing mode. DMA is considered superflous in such 1-5USD processors.

Whereas on the other hand, classical DSP algorithms can tolerate more
output latency and hence given to frame based processing. This would mean
a DMA based buffering technique to generate frames.

I guess, trouble comes when due to increased clocking of ALL silicon, the
2812 nudges the 100-150 MIPS barrier, graduating over a period of time to
be sneaked in to simple DSP applications by smart thinking designers,
instead of a full fledged DSP!

Are you using this to do some video stuff for you, by any chance?

--Bhooshan

Ps:Following is the benchmark results of C2812 in a _frame_ based FIR
processing algorithm of spec: 

Algorithm: 200-tap(nh) low-pass FIR filter
Frame size: 256(nx) 16-bit elements
Sampling frequency: 48KHz


benchmarks:
----------
(nx/2) + (nh+12) + alpha*

*alpha= 36nx/16 = additional *CPU* time to transfer 16 samples to memory
suing an ISR.

Cycles/Frame: 27712

Frames/Sec: 187.5

cycles/Sec:5.20M

#Channels POssible: 28

Redq I/O Rate: 21.5 MBPS

Available SP Rate: 50 MBPS

a DMA engine will be appreciated, especialy when a single channel is
sampled.

The ADC can be set to call the ISR each second conversion NOT WHEN THE
FIFO IS FULL!

And don't forget, the ISR context switch with DSP/BIOS is around 330
cycles.

I guess that the max sampling rate could be 250Ks/sec (with some cpu
spare time for processing).

Nice uC with an ADC at 12.5 MPS :o(

Adrian

Ahhh - the wisdom of the net. Thanks fellows. 

--RY

Steve Underwood wrote:
> Jerry Avins wrote:
>> And the extra latency of waiting for the FIFO to fill can add to the 
>> horror.

> Exactly. I can't think why anyone would want DMA in a control oriented 
> device. You are always trying to keep the processing as close to the 
> metal as possible in control loops.

This is why it's such a fast A/D.  It's not so that you can do 12 
Msamples/second, it's so you can do conversions at maybe 20kHz but get 
the results really quickly.

James.


-- 
James Kennedy
Electronics Design Engineer
Tritium Pty Ltd
Brisbane, Australia

Steve Underwood wrote:

> Randy Yates wrote:
> 
>>> It would be nice to have a part with that core and a DMA engine on the
>>> ADC -- but that would take more silicon, and make it cost more, so I
>>> would have liked it less for my application.
>>
>>
>> Actually, wait a darn minute here. I found yesterday a stripped-down
>> 5501 at 300 MHz for $5. The 2812 is around $15. So tell me why
>> the 2812 is so cheap? Yes, it's got integrated FLASH and A/D, but
>> still ...
>>
>> --RY
> 
> 
> High speed flash is expensive. The serious users of the device are using 
> the masked version, and paying rather less than $15.
> 
> Steve

It's available in masked?  Oooh.  That would explain how they addressed 
the market with a $15 part.

The company where I used was dead serious, but with only a dozen of the 
things in each product, and sales of 100ea/year, masked is out of the 
question.

The flash is astonishingly fast, however, even if you still need to put 
the really critical stuff in RAM.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

Jerry Avins wrote:
> Randy Yates wrote:
>>> Would you rather service an interrupt every sample, or every 16 samples?
>>
>>
>> Um, yes, true. I guess I'm not used to bit-banging like this since the
>> early 80's. So the choice is between M*F MIPS or F MIPS, where
>> F is the sample rate and M is some integer representing the
>> interrupt overhead. Yeah, sure I'd choose F MIPS, but that's still
>> horrible! 
> 
> And the extra latency of waiting for the FIFO to fill can add to the 
> horror.
> 
> Jerry

Exactly. I can't think why anyone would want DMA in a control oriented 
device. You are always trying to keep the processing as close to the 
metal as possible in control loops.

Steve

Randy Yates wrote:
>> It would be nice to have a part with that core and a DMA engine on the
>> ADC -- but that would take more silicon, and make it cost more, so I
>> would have liked it less for my application.
> 
> Actually, wait a darn minute here. I found yesterday a stripped-down
> 5501 at 300 MHz for $5. The 2812 is around $15. So tell me why
> the 2812 is so cheap? Yes, it's got integrated FLASH and A/D, but
> still ...
> 
> --RY

High speed flash is expensive. The serious users of the device are using 
the masked version, and paying rather less than $15.

Steve

Randy Yates wrote:
>>Would you rather service an interrupt every sample, or every 16 samples?
> 
> 
> Um, yes, true. I guess I'm not used to bit-banging like this since the
> early 80's. So the choice is between M*F MIPS or F MIPS, where
> F is the sample rate and M is some integer representing the
> interrupt overhead. Yeah, sure I'd choose F MIPS, but that's still
> horrible! 

And the extra latency of waiting for the FIFO to fill can add to the horror.

Jerry
-- 
Engineering is the art of making what you want from things you can get.
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