Roman Rumian <usun_torumian@agh.edu.pl> wrote in news:e5h8cm$tc0$1
@news.agh.edu.pl:

> Hi friends,
> 
> want to use ADSP-21369 device for universal module containing 
processor, 
> FLASh and SDRAM memory only, but the samples of this device are not 
> available now, so my distributor has sent me ADSP-21364 one.
> 
> In my audio implementations I need 2 seconds delay buufer for many 
> channels, so 1 megaword is a minimum. As I  know from the user manual 
> ADSP-21364 has a parallel memory port, which can be configured as 24 
> address bits and 8 data bits.
> How efficient and easy to use is such a delay buffer construction ?
> 
> Regards
> 
> Roman Rumian
> 

Roman,

Have you looked at our dspblok 21369?

It is a 60mm x 60mm square module with a ADSP-21369, 4Mbit flash, EE 
memory, 64kbit SDRAM and a core switching supply.

It is available independently or as a subcomponent of a dspstak 21369zx2. 
The dspstak 21369zx2 includes a high speed USB interface, programmable 
clocks, RS-232. The dspstak 21369zx2 with ICE includes an ADI EZ-Kit 
sytle debugger and is supported by a free KIT license of VDSP as well as 
a full license.

We have a pilot run completed of both products and will have RoHS 
versions in late June or July.

We have a sufficient number of DSPs to last until the official production 
release of the ADSP-21369 later this year.

Email us for more details/questions.
  

-- 
Al Clark
Danville Signal Processing, Inc.
--------------------------------------------------------------------
Purveyors of Fine DSP Hardware and other Cool Stuff
Available at http://www.danvillesignal.com

Hi friends,

want to use ADSP-21369 device for universal module containing processor, 
FLASh and SDRAM memory only, but the samples of this device are not 
available now, so my distributor has sent me ADSP-21364 one.

In my audio implementations I need 2 seconds delay buufer for many 
channels, so 1 megaword is a minimum. As I  know from the user manual 
ADSP-21364 has a parallel memory port, which can be configured as 24 
address bits and 8 data bits.
How efficient and easy to use is such a delay buffer construction ?

Regards

Roman Rumian