Mike- > I believe that most TI DSPs execute some internal boot > loader code when [or as] they come out of reset. The > c6415 uses a state machine to do the 'reset > configuration' and booting [which usually includes > driving all of the address lines low]. This procedure > would normally be performed in sequential 'chunks' by > a ROM bootloader - in the case of the 6415 everything > that is done at reset time is done in parallel. Right, but we specify "HPI boot" at Reset via config Rs. In that case, we would not expect C641x bootloader to drive address lines or otherwise do anything that messes with the outside world. > For idle processors, I would *expect* that running in > the lowest power mode and exiting it with a reset > would be the best bet. Yes that sounds like the thing to try. -Jeff

Jeff, Just to beat this dead horse one more time... --- Jeff Brower <jbrower@jbro...> wrote: > Mike- > > > > We're working with multiple C6415 board, and > we've > > > noticed that when C641x devices > > > are held in Reset, they actually generate more > heat > > > than when running. The chips > > > work though, and do what they're supposed to > when > > > running (at 720 MHz). > > > > > > This sounds counter-intuitive, and is unlike all > the > > > other Texas Inst DSPs we've > > > worked with. Has anyone else encountered this? > > > > I believe that we observed similar results during > > current testing [although we 'didn't care' about > the > > reset current]. > > :-O > > > I have some personal thoughts concerning the > higher > > current that may be inter-related - > > 1. the reset circuit did not receive the 'low > current > > design scrutiny' that 'normal active' circuitry > > 2. the some of the reset circuitry is only active > > during reset and the cicuitry is not clocked > causing > > higher current consumption. > > 3. during reset clocks may be cut off to other > > portions of the chip causing circuitry that is > > normally clocked to operate in a static state that > > consumes more current. > > > > Although it is customary for many vendors to hold > DSPs > > in reset for extended periods of time, I > personally > > prefer not to do so. A bit of FPGA space to > 'feed' a > > 'branch to self' is my preference. > > Well we're already doing this. We have FPGA logic > that takes DSPs out of Reset on > power-up. Even if host software puts them back in > Reset then there is a time-limit > before the logic takes them out again :-) > > Still I find this surprising, after working with so > many TI DSPs that turn "stone > cold" when held in Reset. I believe that most TI DSPs execute some internal boot loader code when [or as] they come out of reset. The c6415 uses a state machine to do the 'reset configuration' and booting [which usually includes driving all of the address lines low]. This procedure would normally be performed in sequential 'chunks' by a ROM bootloader - in the case of the 6415 everything that is done at reset time is done in parallel. >The practical issue is > what to do if a user needs only X > out of Y DSPs for a particular application, and > needs to minimize power consumption. > I think at this point we can focus on experimenting > with power-down modes to find the > absolute minimum for a populated device. For idle processors, I would *expect* that running in the lowest power mode and exiting it with a reset would be the best bet. mikedunn > > Thanks Mike. > > -Jeff > c6x-unsubscribe@c6x-...

Mike- > > We're working with multiple C6415 board, and we've > > noticed that when C641x devices > > are held in Reset, they actually generate more heat > > than when running. The chips > > work though, and do what they're supposed to when > > running (at 720 MHz). > > > > This sounds counter-intuitive, and is unlike all the > > other Texas Inst DSPs we've > > worked with. Has anyone else encountered this? > > I believe that we observed similar results during > current testing [although we 'didn't care' about the > reset current]. :-O > I have some personal thoughts concerning the higher > current that may be inter-related - > 1. the reset circuit did not receive the 'low current > design scrutiny' that 'normal active' circuitry > 2. the some of the reset circuitry is only active > during reset and the cicuitry is not clocked causing > higher current consumption. > 3. during reset clocks may be cut off to other > portions of the chip causing circuitry that is > normally clocked to operate in a static state that > consumes more current. > > Although it is customary for many vendors to hold DSPs > in reset for extended periods of time, I personally > prefer not to do so. A bit of FPGA space to 'feed' a > 'branch to self' is my preference. Well we're already doing this. We have FPGA logic that takes DSPs out of Reset on power-up. Even if host software puts them back in Reset then there is a time-limit before the logic takes them out again :-) Still I find this surprising, after working with so many TI DSPs that turn "stone cold" when held in Reset. The practical issue is what to do if a user needs only X out of Y DSPs for a particular application, and needs to minimize power consumption. I think at this point we can focus on experimenting with power-down modes to find the absolute minimum for a populated device. Thanks Mike. -Jeff

Hello Jeff, Please see my comments below. mikedunn --- Jeff Brower <jbrower@jbro...> wrote: > > We're working with multiple C6415 board, and we've > noticed that when C641x devices > are held in Reset, they actually generate more heat > than when running. The chips > work though, and do what they're supposed to when > running (at 720 MHz). > > This sounds counter-intuitive, and is unlike all the > other Texas Inst DSPs we've > worked with. Has anyone else encountered this? I believe that we observed similar results during current testing [although we 'didn't care' about the reset current]. I have some personal thoughts concerning the higher current that may be inter-related - 1. the reset circuit did not receive the 'low current design scrutiny' that 'normal active' circuitry 2. the some of the reset circuitry is only active during reset and the cicuitry is not clocked causing higher current consumption. 3. during reset clocks may be cut off to other portions of the chip causing circuitry that is normally clocked to operate in a static state that consumes more current. Although it is customary for many vendors to hold DSPs in reset for extended periods of time, I personally prefer not to do so. A bit of FPGA space to 'feed' a 'branch to self' is my preference. > > -Jeff > c6x-unsubscribe@c6x-... >