Federica,
The CPU does not know that there will be 15 more
write accesses to
consecutive SDRAM addresses when it receives its first write word access
request. And so CPU probably makes a single word write request to SDRAM
(through DMA) every time.
If you can instead write the data to SRAM address
space and then program
EDMA to make a block transfer (in your case, 16 words) from SRAM space
to
SDRAM space, you should only see 4 (and not 16) accesses.
I guess in your example, SDRAM space is non-cacheable
or else the CPU
(through DMA) would have first asked a cache line size of data from
SDRAM
(64 bytes => 16 memory accesses, each of 4 words).
Subrangshu
fedelegger wrote:
Hi,
I'm having problems accessing SDRAM in a reasonable time. I read on
the periperal guide that consequent access to SDRAM should happen in
bursts of 4 words. I understood they are talking about 32-bit words.
Is this correct? Because I tried to look at the signals (Chip enable,
write enable, read enable) with the oscilloscope, but I cannot see
any
burst!
I wrote simple assembler code to write 16 words to SDRAM, and I
observe 16 memory accesses (expected 16/4=4). Each memory access takes
1 EMIF clock cycle. The time between each access is about 10 EMIF clock
cycles. I don't understand what the dsp is doing during tha time. Has
anybody else experienced problems like this with memory access? Am
I
doing anything wrong?
TIA Federica Legger
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