Reply by robertdenardo ●December 20, 20012001-12-20
Eli,

Check what the setting is of the DIVFCT bitfield in the BSCR
register. By default, it is set so that CLKOUT=CPU_CLK/4. The
external memory I/F will run at the CLKOUT speed, so any I/O accesses
will be slower than on the 5402. If you set DIVFCT to 0, CLKOUT will
be the same speed as the 5402. Also, make sure you have the I/O wait
states in SWWSR set to 0.

-Robert --- In c54x@y..., "elismile" <elismile@y...> wrote:
> Hi All,
>
> I ran some application on the 5402, which runs with tight timing
(80%
> processor usage).
>
> The application depends on on-chip RAM only in both processors.
>
> Then I migrated to 5416. I did it the "stupid way": Just took the
> code bundle, made some changes relevant to I/O peripherals, and ran.
>
> The code runs about twice as SLOW on the 5416. Both procssors are
fed
> with the same clock (10 MHz), and both have 9007h on the CLKMD
> register, which means that they both multiply by 10, giving a 100
MHz
> CPU clock. Or...?
>
> The comparison was made by taking away any waiting for I/O
> peripherals, and letting the code run freely. Toggling an I/O pin
> high and low every time the code completed a loop made the running
> time visible on an oscilloscope (electrical engineers or not?).
>
> CCS' timing profile gives the same results on both processors for
> similar pieces of code (well, this clue should be taken with a bit
of
> sceptisism, since the profilings were done with different versions
of
> CCS).
>
> The link map wasn't changed, but as far as I know, the DARAMs are
> organized the same in the lower area.
>
> So dear group, have you any idea of why this can be?
>
> Thanks in advance,
>
> Eli




Reply by elismile ●December 17, 20012001-12-17
Hi All,

I ran some application on the 5402, which runs with tight timing (80%
processor usage).

The application depends on on-chip RAM only in both processors.

Then I migrated to 5416. I did it the "stupid way": Just took the
code bundle, made some changes relevant to I/O peripherals, and ran.

The code runs about twice as SLOW on the 5416. Both procssors are fed
with the same clock (10 MHz), and both have 9007h on the CLKMD
register, which means that they both multiply by 10, giving a 100 MHz
CPU clock. Or...?

The comparison was made by taking away any waiting for I/O
peripherals, and letting the code run freely. Toggling an I/O pin
high and low every time the code completed a loop made the running
time visible on an oscilloscope (electrical engineers or not?).

CCS' timing profile gives the same results on both processors for
similar pieces of code (well, this clue should be taken with a bit of
sceptisism, since the profilings were done with different versions of
CCS).

The link map wasn't changed, but as far as I know, the DARAMs are
organized the same in the lower area.

So dear group, have you any idea of why this can be?

Thanks in advance,

Eli