Reply by July 4, 20042004-07-04
Email to the address listed in your post bounces...

Robert

"Peter Choi" <choi@mecca.ca> wrote:

>Hello, > >The problem with TI (maybe with other DSP manufacturer too I don't know) is >that they don't appear to have a coherent location for their reading >materials. I downloaded the DSK API, the chip API, and a bunch of other >guides but none contain the material I needed. Sure some do talk about the >TIMER API but not in as detailed a format as the link you provided. > >Regards > ><r_obert@REMOVE_THIS.hotmail.com> wrote in message >news:tcl1e09qaov2k9oq7jthgq05atbrdl8u7l@4ax.com... >> "Peter Choi" <choi@mecca.ca> wrote: >> >> >Hello, >> > >> >So I'm a bit confused here. Someone said the timer counts at 1/4 rate of >> >the CPU clock but you said it can be at a rate of 1 or 2. How can I >> >> I say that there can be 1 or 2 "CPU clock cycles per timer count", >> which is the same as saying that the timer counts at either the same >> rate as the CPU clock, or 1/2. This can be right for some processors, >> but maybe 1/4 is the answer for the 6711. I do not recall. However, >> you should learn to reference the literature to be certain yourself. >> Go to www.ti.com, and search the literature for the 6711. There are >> documents that talk about the timer specifically, and will tell you >> exactly what it is. >> >> >determine this? There must be a register that set this divider. >> >> I am not sure if it is settable. Maybe not. Once again, you are >> encouraged to reference the material from TI. >> >> In just a little bit of looking, I found this, which should contain >> the information you are looking for: >> >> http://focus.ti.com/lit/ug/spru582a/spru582a.pdf >> >> Regards, >> >> Robert >> >> www.gldsp.com >> >> >> >> ( modify address for return email ) >> >> www.numbersusa.com >> www.americanpatrol.com >
( modify address for return email ) www.numbersusa.com www.americanpatrol.com
Reply by Peter Choi June 29, 20042004-06-29
Hello,

The problem with TI (maybe with other DSP manufacturer too I don't know) is
that they don't appear to have a coherent location for their reading
materials.  I downloaded the DSK API, the chip API, and a bunch of other
guides but none contain the material I needed.  Sure some do talk about the
TIMER API but not in as detailed a format as the link you provided.

Regards

<r_obert@REMOVE_THIS.hotmail.com> wrote in message
news:tcl1e09qaov2k9oq7jthgq05atbrdl8u7l@4ax.com...
> "Peter Choi" <choi@mecca.ca> wrote: > > >Hello, > > > >So I'm a bit confused here. Someone said the timer counts at 1/4 rate of > >the CPU clock but you said it can be at a rate of 1 or 2. How can I > > I say that there can be 1 or 2 "CPU clock cycles per timer count", > which is the same as saying that the timer counts at either the same > rate as the CPU clock, or 1/2. This can be right for some processors, > but maybe 1/4 is the answer for the 6711. I do not recall. However, > you should learn to reference the literature to be certain yourself. > Go to www.ti.com, and search the literature for the 6711. There are > documents that talk about the timer specifically, and will tell you > exactly what it is. > > >determine this? There must be a register that set this divider. > > I am not sure if it is settable. Maybe not. Once again, you are > encouraged to reference the material from TI. > > In just a little bit of looking, I found this, which should contain > the information you are looking for: > > http://focus.ti.com/lit/ug/spru582a/spru582a.pdf > > Regards, > > Robert > > www.gldsp.com > > > > ( modify address for return email ) > > www.numbersusa.com > www.americanpatrol.com
Reply by June 28, 20042004-06-28
"Peter Choi" <choi@mecca.ca> wrote:

>Hello, > >So I'm a bit confused here. Someone said the timer counts at 1/4 rate of >the CPU clock but you said it can be at a rate of 1 or 2. How can I
I say that there can be 1 or 2 "CPU clock cycles per timer count", which is the same as saying that the timer counts at either the same rate as the CPU clock, or 1/2. This can be right for some processors, but maybe 1/4 is the answer for the 6711. I do not recall. However, you should learn to reference the literature to be certain yourself. Go to www.ti.com, and search the literature for the 6711. There are documents that talk about the timer specifically, and will tell you exactly what it is.
>determine this? There must be a register that set this divider.
I am not sure if it is settable. Maybe not. Once again, you are encouraged to reference the material from TI. In just a little bit of looking, I found this, which should contain the information you are looking for: http://focus.ti.com/lit/ug/spru582a/spru582a.pdf Regards, Robert www.gldsp.com ( modify address for return email ) www.numbersusa.com www.americanpatrol.com
Reply by Peter Choi June 28, 20042004-06-28
Hello,

So I'm a bit confused here.  Someone said the timer counts at 1/4 rate of
the CPU clock but you said it can be at a rate of 1 or 2.  How can I
determine this?  There must be a register that set this divider.

Thanks

<r_obert@REMOVE_THIS.hotmail.com> wrote in message
news:b9i4d01rlpvpju5ob24d1k17c9rn63nfrk@4ax.com...
> "Peter Choi" <choi@mecca.ca> wrote: > > >Hello, > >Am reading the TIMER API for the C6711 device. For the following code,
is
> >it in 16 milliseconds or what? > >"TIMER_setPeriod(hTimer,0x00010000);" > > It depends on the clock rate of the processor, and how many DSP clock > cycles increment the timer. After the counts represented by > 0x00010000 are done by the timer, it will reset to 0. > > The time should be something like this: > > ( 1.0 / DSP clock ) * ( period setting ) * ( DSP clock cycles > per timer count ) > > The second one is your 0x00010000, and the third value can sometimes > be 1 or 2. > > Robert > > www.gldsp.com > > ( modify address for return email ) > > www.numbersusa.com > www.americanpatrol.com
Reply by June 17, 20042004-06-17
"Peter Choi" <choi@mecca.ca> wrote:

>Hello, >Am reading the TIMER API for the C6711 device. For the following code, is >it in 16 milliseconds or what? >"TIMER_setPeriod(hTimer,0x00010000);"
It depends on the clock rate of the processor, and how many DSP clock cycles increment the timer. After the counts represented by 0x00010000 are done by the timer, it will reset to 0. The time should be something like this: ( 1.0 / DSP clock ) * ( period setting ) * ( DSP clock cycles per timer count ) The second one is your 0x00010000, and the third value can sometimes be 1 or 2. Robert www.gldsp.com ( modify address for return email ) www.numbersusa.com www.americanpatrol.com
Reply by Piyush Kaul June 17, 20042004-06-17
Depends on what is the input for the timer. If is is set to internal
clock, the timer counts at the rate 1/4 to the CPU clock. So if your
CPU clock is 200 MHz it means ( 0x10000 x 4) cycles, or ( 0x10000 x 4 
/ 200M ) seconds  = 1.3 seconds.
TINP or TOUT pins are used only when you want to take the timer input
externally or send the timer output to external pin.

Regards
Piyush


"Peter Choi" <choi@mecca.ca> wrote in message news:<PZ9Ac.738545$Pk3.5503@pd7tw1no>...
> Hello, > Am reading the TIMER API for the C6711 device. For the following code, is > it in 16 milliseconds or what? > "TIMER_setPeriod(hTimer,0x00010000);" > > Also, what is this "TIMER_setDatOut" and TINP pin for?
Reply by Peter Choi June 17, 20042004-06-17
Hello,
Am reading the TIMER API for the C6711 device.  For the following code, is
it in 16 milliseconds or what?
"TIMER_setPeriod(hTimer,0x00010000);"

Also, what is this "TIMER_setDatOut" and TINP pin for?