Next question, do I need to call the function CACHE_resetEMIFA(); ?

If I need to run it again, do I run it after the first two CACHE calls?

I am not certain if it is needed or not. Is anything needed beyond the
two calls that I listed earlier?

I am running these calls when my program boots, to set up the
environment correctly, and then not calling them again unless the
processor gets reset and boots again.

Andrew Elder wrote:
> William,
>
> You are 100% correct. Docs do indicate that CACHE_enableCaching() sets
> the appropriate MAR registers. Sorry about that !
>
> - Andrew E.
>
> William C Bonner wrote:
>> Earlier in the thread I mentioned that I was enabling the cache with the
>> following CSL commands. Do they take care of the MAR setting that you
>> are referring to? I think they do, from reading the CSL docs (Page 2-9
>> of document SPRU401i.pdf) The only reason that I list the memory in my
>> linker file is just so that I've got my reference of all of the possible
>> resources on my system.
>>
>> CSL_init();
>> CACHE_setL2Mode(CACHE_64KCACHE);// Sets the Caching mode to use 64k of
>> dsp ram.
>> CACHE_enableCaching(CACHE_CE00);// Enable caching for range CACHE_CE00
>> -(0x80000000 to 0x80FFFFFF)
>>
>> Wim.
>>
>> Andrew Elder wrote:
>>
>>> Hi William,
>>>
>>> Also verify the MAR (Memory Attribute Register) settings for the CE
>>> space that you want to cache are correct.
>>>
>>> - Andrew E.
>>>
>>> Andrew Nesterov wrote:
>>>
>>>> Hi William,
>>>>
>>>>
>>>>
>>>>> Date: Fri, 24 Mar 2006 08:39:45 -0800
>>>>> From: William C Bonner
>>>>> Subject: Enabling and using the caching on tms320c6713 using the Chip
>>>>> Support Library.
>>>>>
>>>>> My understanding about the caching is that it should be transparent to
>>>>> the program once it is turned on. Is that correct? Is there anything
>>>>> that I need to do related to the cache except enable it, and avoid
>>>>> directly using ram in the address range: CACHE : org = 0x00030000,
>>>>> len = 0x00010000
>>>>>
>>>>>
>>>> This is correct and no, you do not need to specify the cache address range,
>>>> as it does not really exists.
>>>>
>>>> Regards,
>>>>
>>>> Andrew
>>>>
>>>>
>>>>
>>>>> MEMORY
>>>>> {
>>>>> VECT : org = 0x00000000, len = 0x00000200
>>>>> IRAM : org = 0x00001300, len = 0x0002ED00
>>>>> CACHE : org = 0x00030000, len = 0x00010000 /* this line is not needed */
>>>>> SRAM : org = 0x80000000, len = 0x00100000
>>>>> }
>>>>>
>>>>> Start a New Thread

William,

You are 100% correct. Docs do indicate that CACHE_enableCaching() sets
the appropriate MAR registers. Sorry about that !

- Andrew E.

William C Bonner wrote:

>Earlier in the thread I mentioned that I was enabling the cache with the
>following CSL commands. Do they take care of the MAR setting that you
>are referring to? I think they do, from reading the CSL docs (Page 2-9
>of document SPRU401i.pdf) The only reason that I list the memory in my
>linker file is just so that I've got my reference of all of the possible
>resources on my system.
>
>CSL_init();
>CACHE_setL2Mode(CACHE_64KCACHE);// Sets the Caching mode to use 64k of
>dsp ram.
>CACHE_enableCaching(CACHE_CE00);// Enable caching for range CACHE_CE00
>-(0x80000000 to 0x80FFFFFF)
>
>Wim.
>
>Andrew Elder wrote:
>
>
>>Hi William,
>>
>>Also verify the MAR (Memory Attribute Register) settings for the CE
>>space that you want to cache are correct.
>>
>>- Andrew E.
>>
>>Andrew Nesterov wrote:
>>
>>
>>>Hi William,
>>>
>>>
>>>
>>>
>>>>Date: Fri, 24 Mar 2006 08:39:45 -0800
>>>>From: William C Bonner
>>>>Subject: Enabling and using the caching on tms320c6713 using the Chip
>>>> Support Library.
>>>>
>>>>My understanding about the caching is that it should be transparent to
>>>>the program once it is turned on. Is that correct? Is there anything
>>>>that I need to do related to the cache except enable it, and avoid
>>>>directly using ram in the address range: CACHE : org = 0x00030000,
>>>>len = 0x00010000
>>>>
>>>>
>>>>
>>>This is correct and no, you do not need to specify the cache address range,
>>>as it does not really exists.
>>>
>>>Regards,
>>>
>>>Andrew
>>>
>>>
>>>
>>>
>>>>MEMORY
>>>>{
>>>> VECT : org = 0x00000000, len = 0x00000200
>>>> IRAM : org = 0x00001300, len = 0x0002ED00
>>>> CACHE : org = 0x00030000, len = 0x00010000 /* this line is not needed */
>>>> SRAM : org = 0x80000000, len = 0x00100000
>>>>}
>>>>
>>>>Thanks. Wim.
>>>>
>>>>
>>>>
> Start a New Thread

Earlier in the thread I mentioned that I was enabling the cache with the
following CSL commands. Do they take care of the MAR setting that you
are referring to? I think they do, from reading the CSL docs (Page 2-9
of document SPRU401i.pdf) The only reason that I list the memory in my
linker file is just so that I've got my reference of all of the possible
resources on my system.

CSL_init();
CACHE_setL2Mode(CACHE_64KCACHE);// Sets the Caching mode to use 64k of
dsp ram.
CACHE_enableCaching(CACHE_CE00);// Enable caching for range CACHE_CE00
-(0x80000000 to 0x80FFFFFF)

Wim.

Andrew Elder wrote:
> Hi William,
>
> Also verify the MAR (Memory Attribute Register) settings for the CE
> space that you want to cache are correct.
>
> - Andrew E.
>
> Andrew Nesterov wrote:
>> Hi William,
>>
>>
>>> Date: Fri, 24 Mar 2006 08:39:45 -0800
>>> From: William C Bonner
>>> Subject: Enabling and using the caching on tms320c6713 using the Chip
>>> Support Library.
>>>
>>> My understanding about the caching is that it should be transparent to
>>> the program once it is turned on. Is that correct? Is there anything
>>> that I need to do related to the cache except enable it, and avoid
>>> directly using ram in the address range: CACHE : org = 0x00030000,
>>> len = 0x00010000
>>>
>>
>> This is correct and no, you do not need to specify the cache address range,
>> as it does not really exists.
>>
>> Regards,
>>
>> Andrew
>>
>>
>>> MEMORY
>>> {
>>> VECT : org = 0x00000000, len = 0x00000200
>>> IRAM : org = 0x00001300, len = 0x0002ED00
>>> CACHE : org = 0x00030000, len = 0x00010000 /* this line is not needed */
>>> SRAM : org = 0x80000000, len = 0x00100000
>>> }
>>>
>>> Thanks. Wim.
>>> Start a New Thread

Hi William,

Also verify the MAR (Memory Attribute Register) settings for the CE
space that you want to cache are correct.

- Andrew E.

Andrew Nesterov wrote:

>Hi William,
>
>
>
>>Date: Fri, 24 Mar 2006 08:39:45 -0800
>>From: William C Bonner
>>Subject: Enabling and using the caching on tms320c6713 using the Chip
>> Support Library.
>>
>>My understanding about the caching is that it should be transparent to
>>the program once it is turned on. Is that correct? Is there anything
>>that I need to do related to the cache except enable it, and avoid
>>directly using ram in the address range: CACHE : org = 0x00030000,
>>len = 0x00010000
>>
>>This is correct and no, you do not need to specify the cache address range,
>as it does not really exists.
>
>Regards,
>
>Andrew
>
>
>
>>MEMORY
>>{
>> VECT : org = 0x00000000, len = 0x00000200
>> IRAM : org = 0x00001300, len = 0x0002ED00
>> CACHE : org = 0x00030000, len = 0x00010000 /* this line is not needed */
>> SRAM : org = 0x80000000, len = 0x00100000
>>}
>>
>>Thanks. Wim.
>>
>>
>>
>
> Start a New Thread

Hi William,

> Date: Fri, 24 Mar 2006 08:39:45 -0800
> From: William C Bonner
> Subject: Enabling and using the caching on tms320c6713 using the Chip
> Support Library.
>
> My understanding about the caching is that it should be transparent to
> the program once it is turned on. Is that correct? Is there anything
> that I need to do related to the cache except enable it, and avoid
> directly using ram in the address range: CACHE : org = 0x00030000,
> len = 0x00010000

This is correct and no, you do not need to specify the cache address range,
as it does not really exists.

Regards,

Andrew

> MEMORY
> {
> VECT : org = 0x00000000, len = 0x00000200
> IRAM : org = 0x00001300, len = 0x0002ED00
> CACHE : org = 0x00030000, len = 0x00010000 /* this line is not needed */
> SRAM : org = 0x80000000, len = 0x00100000
> }
>
> Thanks. Wim.
> Start a New Thread

My understanding of the tms320c6713 processor is that it has 256k of L2
ram that can either be completely addressable, or segmented with the top
64k being used as cache, leaving 192k of directly addressable ram. That
is the way I'm trying to use the processor.

When my process boots, I run the following commands. I'd like to know
if I'm running them in the correct order, or if the order matters, and
if there are any commands that I need to use that I'm not using.

My linker memory map explicitly only uses the first 192k of ram. I have
1 megabyte of sram located at address 0x80000000.

CSL_init();
CACHE_setL2Mode(CACHE_64KCACHE);// Sets the Caching mode to use 64k of
dsp ram.
CACHE_enableCaching(CACHE_CE00);// Enable caching for range CACHE_CE00
-(0x80000000 to 0x80FFFFFF)

My understanding about the caching is that it should be transparent to
the program once it is turned on. Is that correct? Is there anything
that I need to do related to the cache except enable it, and avoid
directly using ram in the address range: CACHE : org = 0x00030000,
len = 0x00010000
Thanks. Wim. Start a New Thread