Yes 50 Mhz onboard pre-filter. The DC sampling rate is 100Mhz, the FPGA
user clock is 100MHz - Every second clock I output an output sample ?
sorry, I couldn't find my post and had to do a search..
Tamara...
>
>
>On Jan 24, 9:41 am, "Tamara" <t...@naic.edu> wrote:
>> Hello...
>>
>> I created a polyphase filter filter based on F.Harris's book shared
>> register design. This is a Decimation by 2, 100 tap, Fs =100MHz, Low
pass
>> 20MHz - stop band 24MHz filter. Each MAC is 28-bit length, 14-bit
ADC
>> input, and the filter output is truncated.
>>
>> I also created a Xilinx distributed arith filter to compare using the
same
>> filter coefficients. ( For some reason I could not get simulations
nor
>> implentation to work with the Xilinx MAC filter).
>>
>> I have an evaluation board with a DAC(14-bit) - The filter looks like
it's
>> working, starts attenuating a 21 MHz signal, at 25MHz, it is
completely
>> down - but then.. I keep increasing the input frequency and signal is
>> being introduced. This does not happen in the Xilinx filter.
>>
>> Can any one give me a clue why this is happening?? I have scaled the
>> quantized filter coefficients to 0.9 calculated by Matlab... I tried
>> rounding and clamping but the output was garbage...
>>
>> Thanks so much. Tamara...
>
>Do you have aliasing? Do you have the appropriate anti-aliasing filter
>for
>your ADC's sampling rate?
>
>
Reply by julius●January 24, 20072007-01-24
On Jan 24, 9:41 am, "Tamara" <t...@naic.edu> wrote:
> Hello...
>
> I created a polyphase filter filter based on F.Harris's book shared
> register design. This is a Decimation by 2, 100 tap, Fs =100MHz, Low pass
> 20MHz - stop band 24MHz filter. Each MAC is 28-bit length, 14-bit ADC
> input, and the filter output is truncated.
>
> I also created a Xilinx distributed arith filter to compare using the same
> filter coefficients. ( For some reason I could not get simulations nor
> implentation to work with the Xilinx MAC filter).
>
> I have an evaluation board with a DAC(14-bit) - The filter looks like it's
> working, starts attenuating a 21 MHz signal, at 25MHz, it is completely
> down - but then.. I keep increasing the input frequency and signal is
> being introduced. This does not happen in the Xilinx filter.
>
> Can any one give me a clue why this is happening?? I have scaled the
> quantized filter coefficients to 0.9 calculated by Matlab... I tried
> rounding and clamping but the output was garbage...
>
> Thanks so much. Tamara...
Do you have aliasing? Do you have the appropriate anti-aliasing filter
for
your ADC's sampling rate?
Reply by Tamara●January 24, 20072007-01-24
Hello...
I created a polyphase filter filter based on F.Harris's book shared
register design. This is a Decimation by 2, 100 tap, Fs =100MHz, Low pass
20MHz - stop band 24MHz filter. Each MAC is 28-bit length, 14-bit ADC
input, and the filter output is truncated.
I also created a Xilinx distributed arith filter to compare using the same
filter coefficients. ( For some reason I could not get simulations nor
implentation to work with the Xilinx MAC filter).
I have an evaluation board with a DAC(14-bit) - The filter looks like it's
working, starts attenuating a 21 MHz signal, at 25MHz, it is completely
down - but then.. I keep increasing the input frequency and signal is
being introduced. This does not happen in the Xilinx filter.
Can any one give me a clue why this is happening?? I have scaled the
quantized filter coefficients to 0.9 calculated by Matlab... I tried
rounding and clamping but the output was garbage...
Thanks so much. Tamara...