Guy,
It could be that the below gets compiled to an optimized loop that has
interrupts turned off while it runs.
do
{
/* nothing */
}while(!transferComplete);
I would look at the ASM output as a first step and then review options.
You can tell the compiler not to generate pipelined loops for this
particular module, or you tell it to only disble interrupts for some
maximum number of cycles. You'll have to look up the specific options
since I don't recall them exactly.
- Andrew E.
Guy Eschemann wrote:
> Hi,
> I'm using EDMA to transfer a block of data from external to internal
> memory. I've setup the EDMA with the proper parameters, set the TCC,
> enabled the TCINT, etc... I've also defined an interrupt service
> routine, which sets a "transferComplete" variable to 1 to notify the
> processing task that new data is available. I registered this ISR into
> the "Hardware Interrupt Service Routine Manager", and enabled the
> dispatching.
>
> In my processing task, I've got the following code which waits for
> this transferComplete variable to be set:
>
> do
> {
> /* nothing */
> }while(!transferComplete);
>
> Well, that doesn't work. The transferComplete variable never gets set,
> and I couldn't figure out why until now, that's why I'm
posting. I
> just noticed that if I do the following:
>
> do
> {
> TSK_sleep(1);
> }while(!transferComplete);
>
> Then then interrupt service routine gets called and everything works
> fine, but:
> - the execution takes more time than it should because of TSK_sleep()
> - I don't know why this works
>
> Any ideas?
> Many thanks,
> Guy.
>
>
>