Hello,
As per my knowledge,the difference is due to CPU Memory
stalls(Memory Bank Conflict). If two values which have to be loaded
simultaneously are in the same memory bank,there will be single CPU STALL. By
using the pragma DATA_MEM_BANK we can avoid these STALLS to some extent.
Another reason is Cache misses. L1D and L1P cache misses also will increase the
cycles. When cache profiling is done on simulator ,u can find the number of data
and program cache misses. By doing cache optimization these misses can be
reduced.
regards
bharath
Swaminathan Sathappan wrote:
Hi everyone,
When I profile the same code in simulator(6416 Functional Simulator) and DSK
(TMS320c6416), the difference in MIPS(Million Instructions Per Cycle) between
the two is 1.0.Hardware board is consuming more cycles (higher MIPS) than the
simulator. What could be the reason??
Swaminathan.S
India.
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