Hello, 

I'm experimenting troubles connecting a C6713 DSK board to a Cypress FX2LP
chip (Eval board) through I2C.

The C6713 I2C module 0 is configured as a slave receiver, and the Cypress
chip as Master transmitter, with a clock at 100kHz. 7bit addressing is
used.

Two pullup resistors of 2,2kohm are set on the SCL0 and SDA0 lines, as
recommanded by the Cypress FX2P doc. And the GNDs of the two boards are
linked. 

The Cypress FX2LP firmware is programmed to send first a start condition,
followed by a control byte, and then send regularly a data byte. The DSP
is simply supposed to store these data bytes in its memory. 

The problem appears when : 
1/ I run the DSP firmware, and the I2C modules waits for a start
condition. (OK)
2/ then I launch the Cypress FX2LP's firmware : The start condition and
control bytes are well seen by the DSP, than 2 data bytes are acknowledged
nicely. But then the DSP seems to drive low the SDA0 and SCL0 lines, and it
hangs definetely, until a reset through CodeComposer is asked. 
On the other board, the FX2LP is not stuck at all, and continues to try to
send data over the bus. 

It seems that a short circuit is created, and the current measured on the
SCL0 line (thanks to a small 100ohm resistor) when the DSP is stucked, is
about 2,5mA. (much less on the SDA0 line)

And two days before the I2C transmission was all OK, with the same
firmware on the two chips.

In fact I don't understand why the DSP crashes like that after 3 bytes
received.
Is there something wrong on the C6713 (the DSK diagnostic tool says it's
OK) ?
Is there a diagnostic tool I can run to check if everything is OK on the
C6713 I2C module ?
Is there something wrong on the hardware or software configuration ? 
As anyone got some idea ?

Below is the I2C module configuration in the main() of the DSP firmware.


Thank you for your help

Regards, Colin




----------------------------

_I2C_I2CMDR0_FSET(IRS,1);	// I2C enabled
_I2C_I2CMDR0_FSET(NACKMOD,I2C_I2CMDR_NACKMOD_ACK); //ack bit after every
byte _I2C_I2CMDR0_FSET(FREE,I2C_I2CMDR_FREE_RFREE); // clk on breakpoints

_I2C_I2CMDR0_FSET(STT,I2C_I2CMDR_STT_START); // no start condition 
_I2C_I2CMDR0_FSET(STP,I2C_I2CMDR_STP_NONE); // no stop condition 
_I2C_I2CMDR0_FSET(MST,I2C_I2CMDR_MST_SLAVE); //slave mode 
_I2C_I2CMDR0_FSET(TRX,I2C_I2CMDR_TRX_RCV); // receiver 
_I2C_I2CMDR0_FSET(XA,I2C_I2CMDR_XA_7BIT); // use 7bit addressing mode
_I2C_I2CMDR0_FSET(RM,I2C_I2CMDR_RM_REPEAD); //use repeat mode 
_I2C_I2CMDR0_FSET(DLB,I2C_I2CMDR_DLB_NONE); //no loopback 
_I2C_I2CMDR0_FSET(STB,I2C_I2CMDR_STB_NONE); //no start byte mode 
_I2C_I2CMDR0_FSET(FDF,I2C_I2CMDR_FDF_NONE); //disable free data mode 
_I2C_I2CMDR0_FSET(BC,I2C_I2CMDR_BC_BIT8FDF); //8bit send mode 
_I2C_I2CCLKL0_FSET(ICCL,38); // useless for a slave configuration ?
_I2C_I2CCLKH0_FSET(ICCH,38); // useless for a slave configuration ? 
_I2C_I2COAR0_FSET(A,0x2A); // Own address at 0x2A
_I2C_I2CSAR0_FSET(A,0x2A); // useless for a slave configuration ? 




_____________________________________
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