Dear SHARC specialists, recently I watched the Bus Request Lines of four SHARCs 21062 on a Transtech ASP P15. What I finally found on my Logic Analyser is quite confusing to me: SHARC No. 1,2 and 3 behave as described in the manual. I see the arbitration and every "lower" priorized SHARC deasserts it's busrequest signal. The "master" sharc with No. 0 always has a zero on it's BR0 line. As I far as I understand the manual and timing diagrams, the highest priorized DSP (i.e. Sharc 0) wins therefore the busmastership ?! Just to make sure, that no other DSP is granted the bus I wrote a little program, which lets communicate two lower priorized SHARCs via broadcast and direct- slave write. Amazingly the communication takes place, so the lower priorized DSP access the external system bus. I am very happy, the bus access takes place, but I really would like to know what is going on. Did I miss something ? Is it normal in a four-processor environment that Sharc 0 always asserts BR0 ? Any answer is highly appreciated thanks in advance Peter Buschhorn --------------- Peter Buschhorn FernUni Hagen Technische Informatik I ICQ# 49945616 ampr.org dh1ao.ampr.org [44.130.19.29] |