Hi, thanks for ur inputs.. helps me to understand better..

>Hi,
>
>it's hard to say much without knowing more about the hardware. 
>Some general comments nonetheless:
>
>- You may want to think of the problem as two separate "loops" for DC
>suppression. 
>First on the analog side, to get your signal through the ADC without
>clipping. 
>Second digital, to maintain the decision threshold level, for example a
>simple IIR lowpass y[n]=alpha x[n]+(1-alpha)y[n-1], 0 << alpha < 1 to
>track the DC component.
>
>The lower the cutoff frequency of the highpass characteristics on both
>ends, the less distortion is introduced. On analog side, your smallest
>possible corner frequency may be limited by capacitor size. And of
course
>it needs to be of wide enough bandwidth to follow the "DC noise"
>reliably.
>
>In some situations, you may know when to expect a discontinuity in the
DC
>component, for example when going out of standby, or change in
frequency.
>One might switch to a faster time constants for a while, or in the
extreme
>case sample the current value (alpha=1 for one sample) 
>
>Best Regards
>
>Markus
>

Hi,

it's hard to say much without knowing more about the hardware. 
Some general comments nonetheless:

- You may want to think of the problem as two separate "loops" for DC
suppression. 
First on the analog side, to get your signal through the ADC without
clipping. 
Second digital, to maintain the decision threshold level, for example a
simple IIR lowpass y[n]=alpha x[n]+(1-alpha)y[n-1], 0 << alpha < 1 to
track the DC component.

The lower the cutoff frequency of the highpass characteristics on both
ends, the less distortion is introduced. On analog side, your smallest
possible corner frequency may be limited by capacitor size. And of course
it needs to be of wide enough bandwidth to follow the "DC noise"
reliably.

In some situations, you may know when to expect a discontinuity in the DC
component, for example when going out of standby, or change in frequency.
One might switch to a faster time constants for a while, or in the extreme
case sample the current value (alpha=1 for one sample) 

Best Regards

Markus

I will try with root raised cosine FIR to recover the biphase manchester
code. the Fc i am looking at is quite low around 320khz, ADC sampling rate
2.5mhz,i have a 1Mhz analog filter before ADC. 

since i have to use the zero-if architecture, i have no choice but to
solve the DC-offset issue first.

Thanks for your advice.


>seankuay wrote:
>> Hi thanks. I will use the mean of N consecutive samples method,
followed
>> by matching filter perhaps. 
>
>What filter would that be? Another averager? I take it you aren't 
>interested in high frequencies.
>
>Jerry
>-- 
>Engineering is the art of making what you want from things you can get.
>

seankuay wrote:
> Hi thanks. I will use the mean of N consecutive samples method, followed
> by matching filter perhaps. 

What filter would that be? Another averager? I take it you aren't 
interested in high frequencies.

Jerry
-- 
Engineering is the art of making what you want from things you can get.

Hi thanks. I will use the mean of N consecutive samples method, followed
by matching filter perhaps. 

Thanks for your great help.


>
>Seankuay,
>
>Some thoughts:
>
>1. Maybe the mean of N consecutive samples and subtracting the mean
>from the signal helps?
>2. Nice comp.dsp thread
>http://groups.google.com/group/comp.dsp/browse_thread/thread/802e18dacc764eb1/0f2b53e1832ad0b1?lnk=gst&q=dc+removal&rnum=1#0f2b53e1832ad0b1
>3. A Xilinx app note from the above thread
>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_dig_offset
>4. DSPguru: DSP Trick: Fixed-Point DC Blocking Filter With Noise-
>Shaping
>http://www.dspguru.com/comp.dsp/tricks/alg/dc_block.htm
>
>HTH,
>Krishna
>http://dsplog.blogspot.com
>
>

"seankuay" <seankuay@yahoo.com> wrote in message
news:suidnTDc2_vpAjPbnZ2dnUVZ_uCinZ2d@giganews.com...
> Hi Experts,
>
> I am using a zero-IF system now, where the analog mixer output has a
> dynamic/variable DC offset.

Simply put, this approach sucks.

> The analog mixer output is fed into an op-amp
> for amplification(low amplification, no saturation) and finally into ADC.

And this makes it even worse.

> I am currently oversampling the incoming signals.

No point. It is already garbled.

> My problem now is due to
> the variable/dynamic DC offset.

If it would be just your problem, it would not be a big deal. The real
problem is that the SDR sucks regardless of your ignorance.

> his is because i am not able to find a
> neat way of getting the dynamic "comparator Vref" in order to convert the
> signals (437,480,502,476,431...) into a binary sequence of 1-0-1-0-0-1 of
> manchester codes.

Convert your carrier into low IF so the manchester spectral null will fall
into zero frequency. So you can safely remove the DC. Of course the
processing should be complex.


Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com

Seankuay,

Some thoughts:

1. Maybe the mean of N consecutive samples and subtracting the mean
from the signal helps?
2. Nice comp.dsp thread
http://groups.google.com/group/comp.dsp/browse_thread/thread/802e18dacc764eb1/0f2b53e1832ad0b1?lnk=gst&q=dc+removal&rnum=1#0f2b53e1832ad0b1
3. A Xilinx app note from the above thread
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=kc_dig_offset
4. DSPguru: DSP Trick: Fixed-Point DC Blocking Filter With Noise-
Shaping
http://www.dspguru.com/comp.dsp/tricks/alg/dc_block.htm

HTH,
Krishna
http://dsplog.blogspot.com

Hi Experts,

I am using a zero-IF system now, where the analog mixer output has a
dynamic/variable DC offset. The analog mixer output is fed into an op-amp
for amplification(low amplification, no saturation) and finally into ADC.

I am currently oversampling the incoming signals. My problem now is due to
the variable/dynamic DC offset. This is because i am not able to find a
neat way of getting the dynamic "comparator Vref" in order to convert the
signals (437,480,502,476,431...) into a binary sequence of 1-0-1-0-0-1 of
manchester codes.

Questions
==========
**1** Besides performing DC-offset compensation at the analog circuit
before ADC, is there anyway i can perform the dynamic DC-offset
compensation to the signals inside DSP so that i can use a simple
zero-crossing compararison method to derive the binary sequences of
1-0-1-0-1-1-0.....? I have tried implementing a first-order
differentiator-integrator in the DSP, but it seems that the signal will
get distored at the beginning of each block.

**2** Or, is there anyway to solve this issue in DSP besides doing
DC-offset compensation? Is it possible i can find the dynamic/variable
DC-offset as fast as possible so that i can use that DC-offset value as
the "comparator Vref" to derive binary sequences of 1-0-1-0 ?


Please kindly advise. Thanks for your great help.