> Recently, I develop Mpeg4 decoder by using DM642.
Video bitstream was transfered from PC throuth PCI to
> SSDRAM in dm642. The bitstream was a ".avi" file and is of PAL type video. The
frame is of 352*288 pixels(CIF type).
> As we know, to correctly display the video, the output frames should be in
speed of 25 frames per second. While the frame rate
> is a little faster than 25 frames per second. What i have done are as
following: when an frame image(2 fields) has been displayed,
> the vport generates an interrupt to CPU, a vport ISR was configured for it. In
the vport ISR, i have done this(reference to SPRU629E):
What is a "little faster"? What % increase to be precise?
-Jeff
> interrupt void VPDispIsr(void)
> {
> volatile uint32 vpis;
> vpis = (*(volatile uint32*)(0x01c400cc));
>
> if(vpis & 0x2000)
> {
> (*(volatile uint32*)(0x01c40200)) |= 0x40000000; // to clear VDSTAT FRMD
bit
> (*(volatile uint32*)(0x01c400cc)) |= 0x00002000; // to clear VPIS DCMP
bit
> frameContinue = 1; // by using this to trigger another frame decoding in
MAIN()
> // in the main(), a while(1){} waits for frameContine becoming 1
, then start decode.
> }
> if(vpis & 0x1000)
> (*(volatile uint32*)(0x01c400cc)) |= 0x00001000;
> }
>
> I have configured the vport registers in "PAL video type(25 frames per
second)" by referencing to BT656 standard and the example in SPRU629E,
> however, the video displayed was a little faster than the normal 25 frames per
second. I detected the time difference by using a timer(or a watch).
> One possibility I thought is that sometimes the cpu reenter the ISR by a same
interrupt. Because the DCMP bit in VPIS and
> FRMD bit in VDSTAT have been cleard, I am confused by this.
Reply by ●January 23, 20072007-01-23
Jeff:
I designed the card with DM642 600MHz by myself.
An outer crystal of 27 MHz was used to feed the VP0CLK0(PIN AF14) and
VP2CLK0(PIN A7).
You are right, I want to use the interrupt generated by vport to synchronize
the application, and the pertainning steps were done in the ISR.
I will try your advice.
luo guangjun
Reply by ●January 23, 20072007-01-23
Jeff: For example, a file which lasts 5 minutes(played by windows media
player or other video player), will be decoded by the decoder in my application
for 5 minutes and 10 seconds. In the beginning, i didn't find the
difference out. When i compared the quality of the decoded video which decoded
by my decoder and other video player, i got it.
luo guangjun
Reply by Jeff Brower●January 23, 20072007-01-23
Luo Guangjun- > Jeff: For example, a file which lasts 5
minutes(played by windows media player
> or other video player), will be decoded by the decoder in my application for
5
> minutes and 10 seconds. In the beginning, i didn't find the difference
out. When i
> compared the quality of the decoded video which decoded by my decoder and
other
> video player, i got it.
This is with EVM DM642 card? And you're expecting VPORT register status
bits to
control the frame-rate?
If so one thing I would suggest is not to make any assumptions about your ISR
or
other code until you are *sure* it's not the a DM642 reference clock
(external input)
or CPU clock itself that's causing the small difference. You might try
toggling a
GPIO line for each frame and watching it on the scope -- if it's off by 1.6
msec, you
will certainly be able to measure that.
I thought some of the reference oscillators on the EVM DM642 board are
voltage-controlled to allow either 24 fps or 25 fps, so you may need to make
some
adjustment.
-Jeff
Reply by ●January 22, 20072007-01-22
Hi, all
Recently, I develop Mpeg4 decoder by using DM642. Video bitstream was
transfered from PC throuth PCI to
SSDRAM in dm642. The bitstream was a ".avi" file and is of PAL type video. The
frame is of 352*288 pixels(CIF type).
As we know, to correctly display the video, the output frames should be in speed
of 25 frames per second. While the frame rate
is a little faster than 25 frames per second. What i have done are as following:
when an frame image(2 fields) has been displayed,
the vport generates an interrupt to CPU, a vport ISR was configured for it. In
the vport ISR, i have done this(reference to SPRU629E):
if(vpis & 0x2000)
{
(*(volatile uint32*)(0x01c40200)) |= 0x40000000; // to clear VDSTAT FRMD
bit
(*(volatile uint32*)(0x01c400cc)) |= 0x00002000; // to clear VPIS DCMP bit
frameContinue = 1; // by using this to trigger another frame decoding in
MAIN()
// in the main(), a while(1){} waits for frameContine becoming 1 ,
then start decode.
}
if(vpis & 0x1000)
(*(volatile uint32*)(0x01c400cc)) |= 0x00001000;
}
I have configured the vport registers in "PAL video type(25 frames per second)"
by referencing to BT656 standard and the example in SPRU629E,
however, the video displayed was a little faster than the normal 25 frames per
second. I detected the time difference by using a timer(or a watch).
One possibility I thought is that sometimes the cpu reenter the ISR by a same
interrupt. Because the DCMP bit in VPIS and
FRMD bit in VDSTAT have been cleard, I am confused by this.