Reply by Ron N. September 19, 20072007-09-19
On Sep 18, 2:41 pm, "Steve4DSP" <stephen_lea...@hotmail.com> wrote:
> >> - No more than 10mA under load conditions > At a guess i would have said that 100Mips would make the cut easily,
Depending on voltage, what you are asking for is about 4 to 8 "Mips"/mW, which is likely just above what general purpose processors are capable of these days. Dedicated logic for your processing algorithm, either an ASIC or a low-power FPGA, might be one way to get a higher MOPs/mW, by trading off against generality. Generality (e.g. charging and discharging those wires and gate inputs optionally usable by other operations than the ones your specific app needs) costs power. IMHO. YMMV. -- rhn A.T nicholson d.0.t C-o-M
Reply by September 19, 20072007-09-19
On Sep 18, 7:37 pm, "Steve4DSP" <stephen_lea...@hotmail.com> wrote:
> Vladimir, > > Thanks for your post, > > Point taken about the DAC not being integrated, but i dont believe thats > the case for ADC's. > > 50 Mips sounds about right to me, from my rough calculations 100 Mips > would have easily done the job. > > Regarding Standby Power, and Powerdown, I'm still wanting to be able to > wake it up by a GPIO interrupt of some sort (ie, from a keypad scan), so > it still must be awake in some respects, > > Given this point, > ADSP-B531 - Exceeds the 10mA by a further 10mA in low power operation > TMS55xx - Exceeds the 50uA by a further 50uA in sleep with IO Active > > Thanks for you advice. > > Regards, > Stephen Leahey
As others have said, your active power requirements are never going to be met. You're not going to find any current processor that does ~100 MIPS at less than 10 mA. Also, you're probably best served by specifying your power requirements in watts, not amperes. The required core voltage can vary significantly among different parts (maybe 1.1 to 2.0 V or so), and you want an apples-to-apples comparison. Jason
Reply by dalai lamah September 19, 20072007-09-19
Un bel giorno Steve4DSP digit&#4294967295;:

> I should say at this point that i intend to process audio and sample at > 10kHz at least 2 ADC's and 2 DAC's concurrently... > That said, i intend to apply the adaptive echo cancellation to the 2 ADC > inputs > Maybe that would help for a mips estimation...
With FPGAs everything has to do with the number of gates used; Xilinx (the brand I'm more familiar with) has a very precise power simulator, I suppose that Actel has one too. Of course, you will have to extimate how much gates you need; searching between the www.opencores.net projects can give you an idea.
> If your processing ADC/DAC IO's on an FPGA im presuming that you would > have to interface to them externally via an SPI or whatever?
Yes, but you won't find a 100-MIPS DSP with internal DACs either, so this doesn't make much difference anyway. :-) Actually you could syntesize as many ADCs and DACs you want with an FPGA and few external components, by using PWM and/or sigma-delta architecture. You can find some interesting app notes in Xilinx site, IIRC. P.S. Here they are: http://www.xilinx.com/bvdocs/appnotes/xapp155.pdf http://www.xilinx.com/bvdocs/appnotes/xapp154.pdf -- emboliaschizoide.splinder.com
Reply by Martin Thompson September 19, 20072007-09-19
"Steve4DSP" <stephen_leahey@hotmail.com> writes:

> > Regarding Standby Power, and Powerdown, I'm still wanting to be able to > wake it up by a GPIO interrupt of some sort (ie, from a keypad scan), so > it still must be awake in some respects,
How about an MSP430 for the low-power housekeeping stuff, which can switch on a big DSP as and when required? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Reply by Jerry Avins September 18, 20072007-09-18
Steve4DSP wrote:

   ...

> Altough, i could see no ADC, or DAC in the datasheet?
The development board has a codec. I think it's mono, like the one on the 'C31 board. Jerry -- Engineering is the art of making what you want from things you can get. &macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;
Reply by Steve4DSP September 18, 20072007-09-18
Vladimir,

Thanks for your post,

Point taken about the DAC not being integrated, but i dont believe thats
the case for ADC's.

50 Mips sounds about right to me, from my rough calculations 100 Mips
would have easily done the job.

Regarding Standby Power, and Powerdown, I'm still wanting to be able to
wake it up by a GPIO interrupt of some sort (ie, from a keypad scan), so
it still must be awake in some respects,

Given this point,
ADSP-B531   - Exceeds the 10mA by a further 10mA in low power operation
TMS55xx     - Exceeds the 50uA by a further 50uA in sleep with IO Active

Thanks for you advice.

Regards,
Stephen Leahey

Reply by Vladimir Vassilevsky September 18, 20072007-09-18

Steve4DSP wrote:

> Hi > > Im trying to find a DSP that meets a few different requirements.
Get real.
> In short, it has to be the following: > > - <40uA in Standby mode
Standby mode is not much different from the powerdown. You can always toggle the power on/off by hardware.
> - No more than 10mA under load conditions
Unrealistic, especially including the DAC/ADC.
> - 2x ADC's & 2x DAC's (preferablly 3 of both)
DSPs with integrated ADCs and especially DACs are very rare. ADI used to have a 218x DSP with the integrated audio codec for the cellphones.
> - enough Mips or equivalent to process, filter, and apply adaptive echo > cancellation on 2 seperate channels
It depends. Up from 50 MIPS.
> - US$7 per 1ku
A lower end DSP with a lower end CODEC can fit the bill. TMS55xx or BlackFin 53x, TLV320AICxx codec.
> - US$1000 or less for a dev kit
It is about $500 typically.
> The only thing I've found so far is a AMI Belasigna250, but its expensive, > has an expensive dev kit, and is <50uA in standby mode... > > in particular, the sub 40uA standby current must be met, most of the other > stuff is a little more flexible > > Any advice would be greately appreciated.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by Randy Yates September 18, 20072007-09-18
"Steve4DSP" <stephen_leahey@hotmail.com> writes:

> Hi > > Im trying to find a DSP that meets a few different requirements. > > In short, it has to be the following: > > - <40uA in Standby mode > - No more than 10mA under load conditions > - 2x ADC's & 2x DAC's (preferablly 3 of both) > - enough Mips or equivalent to process, filter, and apply adaptive echo > cancellation on 2 seperate channels > - US$7 per 1ku > - US$1000 or less for a dev kit > > The only thing I've found so far is a AMI Belasigna250, but its expensive, > has an expensive dev kit, and is <50uA in standby mode... > > in particular, the sub 40uA standby current must be met, most of the other > stuff is a little more flexible > > Any advice would be greately appreciated. > > Regards, > Stephen Leahey
I'm not sure what an AEC takes in terms of MIPS, but the other requirements point to the TI MSP430 series, in my opinion. I think they're only about 16 MIPS, though. -- % Randy Yates % "With time with what you've learned, %% Fuquay-Varina, NC % they'll kiss the ground you walk %%% 919-577-9882 % upon." %%%% <yates@ieee.org> % '21st Century Man', *Time*, ELO http://home.earthlink.net/~yatescr
Reply by Steve4DSP September 18, 20072007-09-18
>Un bel giorno Steve4DSP digit&#65533;: > >> - <40uA in Standby mode >> - No more than 10mA under load conditions >> - 2x ADC's & 2x DAC's (preferablly 3 of both) >> - enough Mips or equivalent to process, filter, and apply adaptive
echo
>> cancellation on 2 seperate channels >> - US$7 per 1ku >> - US$1000 or less for a dev kit > >It doesn't look too easy. How many MIPS are we talking about? Have you >considered using an FPGA? For example Actel claims a 13uA maximum
current
>drain in sleep mode for its IGLOO family. > >-- >emboliaschizoide.splinder.com >
Hi, Thanks for the post. Interesting idea, i havent considered FPGA's till now because i have never had experience with them... I should say at this point that i intend to process audio and sample at 10kHz at least 2 ADC's and 2 DAC's concurrently... That said, i intend to apply the adaptive echo cancellation to the 2 ADC inputs Maybe that would help for a mips estimation... At a guess i would have said that 100Mips would make the cut easily, but i have never actually used a DSP in an application this intensive, and its such a hardware dependant figure anyway. If your processing ADC/DAC IO's on an FPGA im presuming that you would have to interface to them externally via an SPI or whatever? Regards, Stephen Leahey
Reply by Steve4DSP September 18, 20072007-09-18
>Steve4DSP wrote: >> Hi >> >> Im trying to find a DSP that meets a few different requirements. >> >> In short, it has to be the following: >> >> - <40uA in Standby mode >> - No more than 10mA under load conditions >> - 2x ADC's & 2x DAC's (preferablly 3 of both) >> - enough Mips or equivalent to process, filter, and apply adaptive
echo
>> cancellation on 2 seperate channels >> - US$7 per 1ku >> - US$1000 or less for a dev kit >> >> The only thing I've found so far is a AMI Belasigna250, but its
expensive,
>> has an expensive dev kit, and is <50uA in standby mode... >> >> in particular, the sub 40uA standby current must be met, most of the
other
>> stuff is a little more flexible >> >> Any advice would be greately appreciated. > >Look up TI's 320VC33. I think the development board has a mono codec, >but expansion is fairly easy. > >Jerry >-- >Engineering is the art of making what you want from things you can get. >&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr;&macr; >
Hi Jerry, Thanks for the Tip, I think that the power requirements on this may still be to high. At 20Mhz it would still consume around 20mA, where as the belasigna250 is <5mA, plus the idle2 current is again 50uA, Altough, i could see no ADC, or DAC in the datasheet? This may not be suitable. Thanks anyway.