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You might want to try asynchronous interface where each access has equal number of cycles. Regards, Wilson wrote: >_____________________________________ >Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. > >_____________________________________ >About this discussion group: > >To Join: Send an email to > >To Post: Send an email to > >To Leave: Send an email to > >Archives: http://www.yahoogroups.com/group/c6x > >Other Groups: http://www.dsprelated.com > >There is 1 message in this issue. > >Topics in this digest: > > 1. synchronous FIFO to EMIF of C6202 > From: < >________________________________________________________________________ >________________________________________________________________________ > >Message: 1 > Date: Fri, 21 Jun 2002 09:04:19 +0800 (CST) > From: <> >Subject: synchronous FIFO to EMIF of C6202 > >Hi,everyone. >there are three synchronous FIFO(133MHz) in our system. two link to EMIF of C6202, >and one link to XBus of C6202. but the chip has not glueless FIFO interface. >i want to interface to FIFO as SBSRAM,but the first access to SBSRAM requies >an initial stert-up penalty of two cycles. and the FIFO don't need these two cycles. >please give me some help on this. Thank you! >________________________________________________________________________ >________________________________________________________________________ > >">http://docs.yahoo.com/info/terms/ -- -- //\\\\ | ~ ~ | ( O O ) ___________________________________oOOo______( )_____oOOo_______ Wilson Mai Phone: (613) 562-9936-225 SOMA Networks Inc. Fax: (613) 562-8226 110 Clarence St. Suite 3, Email: Ottawa, Ontario Canada K1N 5P6 Oooo _________________________________________oooO______( )_________ ( ) ) / \ ( (_/ \_) |