Reply by Vladimir Vassilevsky●January 3, 20082008-01-03
HasPer wrote:
> I have a DSP code running on C64x and it is about 30 MIPS (the code
> resides in L2), if I use L2 for some other purposes and the DSP code
> resides in external memory (basically the Program should be
> transferred from External memory to cache whenever is needed), what is
> the effect of this change on the MIPS, is it going to be substantial
> or not.
It depends on the application. However, here are some typical numbers
from my experience:
* Using the external SDRAM for code and data (no caching) is ~15 times
slower then L1 RAM.
* The cached SDRAM is somewhat 10% slower, then L1.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Reply by Nils●January 3, 20082008-01-03
HasPer schrieb:
> I have a DSP code running on C64x and it is about 30 MIPS (the code
> resides in L2), if I use L2 for some other purposes and the DSP code
> resides in external memory (basically the Program should be
> transferred from External memory to cache whenever is needed), what is
> the effect of this change on the MIPS, is it going to be substantial
> or not.
That depends entirely on your program - where it spends most of the time
(in short loops or in control code scattered around some hundret of
kilobytes?). How fast is your external memory? That has an impact as well.
The C64x has an instruction cache that you can enable (most probably it
already is). Small software pipelined loops are loaded into the DSP and
are executed from an internal buffer. So with a bit of luck you may see
very little or no difference in speed at all.
Go and benchmark your code. That's the only way to get reliable answers
to your question.
Nils
Reply by HasPer●January 3, 20082008-01-03
Hi guys,
I have a DSP code running on C64x and it is about 30 MIPS (the code
resides in L2), if I use L2 for some other purposes and the DSP code
resides in external memory (basically the Program should be
transferred from External memory to cache whenever is needed), what is
the effect of this change on the MIPS, is it going to be substantial
or not.
I appreciate any help or comments.
Regards,
HasPer