Riemer-

> We're planning to develop a new board consisting of a Cypress FX2 USB
> controller, an Altera Cyclone2 and a TI C6713 DSP, so this board can be
> used in several student labs.
> I would like to connect the FPGA and DSP to each other using the HPI
> port, so the DSP can be bootloaded and during runtime the FPGA can
> stream data to/from the DSP memory. This would also leave the EMIF port
> available for normal RAM expansion. Is this a valid/safe approach?

That sounds Ok. To boot the DSP you would configure it for HPI boot (via
pull-up/down Rs sampled at Reset), download code via USB from the host PC, move to
DSP mem via HPI32, and run the DSP. The same approach can be used to allow the host
to read/write data to the DSP while it's running.

Richard's suggestion of also hooking EMIF to the FPGA is good. He points out that
dual-port RAM, FIFOs, etc. are straightforward to implement in FPGA logic. Even if
you don't use this connection at first, it could be helpful to have in the design to
support more sophisticated applications.

> I have found very useful information on this site about the connection
> between a DSP and a host using the HPI port, but I haven't found any
> accompanying DSP code yet. Is this because the HPI requests are handled
> not by the CPU, but by the DMA controller on the DSP? If no code is
> needed to initiate HPI transfers, surely some commands are needed to
> set up the HPI port? Can anyone please guide me towards a short example
> on this?

The only DSP code you need is to clear the DSPINT bit after Reset/boot, and possibly
set/clear HINT and DSPINT depending on host-DSP handshaking convention that you
implement in software. HPI is a slave port and driven strictly by the external
(host) processor. There are a couple of advanced cases where you might need "host
driver" code for 6713:

-a few onchip mem areas that HPI can't "reach"

-with L2 cache enabled, the 6713 doesn't snoop
data transferred from HPI to external mem (e.g.
SDRAM)

In those cases you have to transfer data elsewhere in DSP internal mem first, then
run a short ISR that moves the data as needed.

-Jeff

Dear Riemer,

At 06:04 12.06.2007 -0400, r...@gmail.com wrote:
>The idea is that the DSP will get bootloaded by the FPGA through the HPI
>port, and that data can be streamed between FPGA and DSP during runtime
>using the same port, so the EMIF remains free for extra RAM. Is this a
>valid approach?

Yes, but the FPGA must contain a C core that is able to handle USB (I
assume the DSP program should be bootloaded via USB).

>I've found several useful posts on this board/site about the hardware HPI
>connection, but nothing about the code needed. Does this mean the HPI
>requests are not handled by the CPU of the DSP, so no code is needed? If
>that's the case, there probably are some CPU commands needed that
>initialize the HPI interface, can someone please guide me to a small example?

The 6713 HPI is a slave-only port which is completely initialized and
controlled by the host (FPGA in your system), hence no code is required on
the DSP. You can consider the HPI as an additional DMA controller, which is
controlled solely by the host. The only thing the DSP can do is generating
interrupts to the host to get attention.

One drawback of your approach is that the FPGA must know where to read and
write data from/to the DSP. Your DSP programs must use fixed data buffers,
otherwise the FPGA program (or the uC core program in the FPGA) must be
changed accordingly. This may limit the usability for an educational system.
If possible, I would add an additional EMIF interface between FPGA and DSP,
e.g. a small RAM area implemented in the FPGA. This can be used to
communicate data buffer locations and sizes and variable locations to the
FPGA at the start of the DSP program.

Best Regards,
Adolf Klemenz, D.SignT

Hi all,

We are planning to create an educational board that has a Cypress FX2 USB controller, an Altera Cyclone2 FPGA and a TI C6713 DSP, so this board can be used for several different student labs.

The idea is that the DSP will get bootloaded by the FPGA through the HPI port, and that data can be streamed between FPGA and DSP during runtime using the same port, so the EMIF remains free for extra RAM. Is this a valid approach?
I've found several useful posts on this board/site about the hardware HPI connection, but nothing about the code needed. Does this mean the HPI requests are not handled by the CPU of the DSP, so no code is needed? If that's the case, there probably are some CPU commands needed that initialize the HPI interface, can someone please guide me to a small example?

Any help is much appreciated.
Riemer Grootjans
Vrije Universiteit Brussel