> Hi, everyone. I have a problem about the NCO design and hope to get some
> help from this forum.
>
> I need to design a digital timing recovery loop. The architecture
> consists of a Gardner timing error detector, loop filter and NCO. (To my
> best knowledge, such structure is quite classical.) All three building
> blocks shall be implemented in digital domain. The A/D oversampling rate
> is 32. I have no problem with Gardner TED and loop filter, but I have no
> idea how to implement the NCO (numerically controller oscillator). I've
> never worked on NCO before, and so far haven't found any papers delving
> into its details. What I know is that NCO is driven by the loop filter
> output, but I don't know how? Is a NCO a counter which can adjust its
> counting value according to the loop filter output? IF so, how it works,
> for example, what is the adjustment step? How frequently it is adjusted?
> So on...
>
> Can anyone here give me some ideas? Thanks in advance!
The NCO is what you make it.
"Real" NCOs are usually implemented as a phase accumulator to which is
added a frequency command at each clock tick, thereby advancing the
phase. Then the phase accumulator is applied to a sine look-up table and
thence to a DAC (if you want to transition back to the analog domain).
If you just want a clock tick, you can have a clock that counts up to
some limit, and adjust the limit. Here you're adjusting the clock
period, so the frequency will be proportional to the reciprocal of the
command. You can also have the clock count down, and load the period
command whenever it hits zero -- this would take fewer gates to implement
in an FPGA, I suspect, but microcontroller timers more often let you
count up to the limit.
If you're sampling at a fixed interval and you need to interpolate the
data slicing then you'd need to implement something like the phase
accumulator method, but have a way to do interpolation between samples.
--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com
Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html
Reply by Darol Klawetter●January 29, 20082008-01-29
On Jan 28, 8:49�pm, "clari" <iamzhi...@yahoo.com> wrote:
> Hi, everyone. I have a problem about the NCO design and hope to get some
> help from this forum.
>
> I need to design a digital timing recovery loop. The architecture consists
> of a Gardner timing error detector, loop filter and NCO. (To my best
> knowledge, such structure is quite classical.) All three building blocks
> shall be implemented in digital domain. The A/D oversampling rate is 32. I
> have no problem with Gardner TED and loop filter, but I have no idea how to
> implement the NCO (numerically controller oscillator). I've never worked on
> NCO before, and so far haven't found any papers delving into its details.
> What I know is that NCO is driven by the loop filter output, but I don't
> know how? Is a NCO a counter which can adjust its counting value according
> to the loop filter output? IF so, how it works, for example, what is the
> adjustment step? How frequently it is adjusted? So on...
>
> Can anyone here give me some ideas? Thanks in advance!
An NCO can be built with a phase accumulator and sine lookup table.
Typically, the output of the phase accumulator is scaled down to the
match the the address size of the lookup table. The noise of the NCO
is a function of the bit width of the accumulator, the size of the
lookup table, and bit width of the table entries.
The input to the phase accumulator would consist of the sum of a phase
increment corresponding to the nominal lock frequency and a phase
offset that would be determined by the output of your loop filter and
the desired pull range.
This is not all of the detail you want, but it should give you some
idea of how to start.
Darol Klawetter
Reply by clari●January 28, 20082008-01-28
Hi, everyone. I have a problem about the NCO design and hope to get some
help from this forum.
I need to design a digital timing recovery loop. The architecture consists
of a Gardner timing error detector, loop filter and NCO. (To my best
knowledge, such structure is quite classical.) All three building blocks
shall be implemented in digital domain. The A/D oversampling rate is 32. I
have no problem with Gardner TED and loop filter, but I have no idea how to
implement the NCO (numerically controller oscillator). I've never worked on
NCO before, and so far haven't found any papers delving into its details.
What I know is that NCO is driven by the loop filter output, but I don't
know how? Is a NCO a counter which can adjust its counting value according
to the loop filter output? IF so, how it works, for example, what is the
adjustment step? How frequently it is adjusted? So on...
Can anyone here give me some ideas? Thanks in advance!