The decoder is using the upper address lines. The lowest decoded line,
Y0, selects the flash. This is due to A23-A21 = 000, the lowest address.
Boot flash starts at 0x0000....
The ADSP-21262 uses a muxed data and addr bus. For booting in is demuxed
to 24 address lines and 8 data lines using a 74573 type latch or
something equivalent. The EZ Kit uses a 74LVC373 for this purpose. A
74LVC573 is easier to route. We used a PLD for the decoder, latch and
misc functions on our boards for this.
Al Clark
Danville Signal processing, Inc.
"patki.onkar" <patki.onkar@mte-india.com> wrote in
news:LPCdnVneaa_oCjvanZ2dnUVZ_t6onZ2d@giganews.com:
> Hi,
>
> thnaks for reply, but I think you have not got my doubt.
>
> Here I am concerned about "booting of DSP from FLASH" and not about
> the programming of FLASH thorugh emulator.
>
> Your link ===
> http://www.danvillesignal.com/analog-devices-development-tools/sharc-bl
> ackfin-programmer.html talks about the flash programming.
>
> So can you please highlight on Booting of DSP through FLASH and where
> exactly could I find the starting for the BOOT?
>
> And as i have mentioned earlier, in the kit there is a decoder, Y0 of
> which goes to Chip Select of Flash, which means @ booting DSP is
> supposed to make some adresses out on the Address Bus.
>
> Please clarify this.
>
>>Al Clark wrote:
>>
>> ...
>>
>>> BTW, We are releasing a SHARC/Blackfin flsah programmer very soon.
>>> Here
>
>>> is a link:
>>>
>>> http://www.danvillesignal.com/analog-devices-development-tools/sharc-
>>> blackfin-programmer.html
>>
>>Al,
>>
>>Your email software wraps long lines. Mine wraps only at spaces.
>>Here's the link entire:
>>http://www.danvillesignal.com/analog-devices-development-tools/sharc-bl
>>ackfin-programmer.html
>>
>>Jerry
>>--
>>Engineering is the art of making what you want from things you can
>>get.
>>???????????????????????????????????????????????????????????????????????
>>
>
Reply by patki.onkar●February 4, 20082008-02-04
Hi,
thnaks for reply, but I think you have not got my doubt.
Here I am concerned about "booting of DSP from FLASH" and not about the
programming of FLASH thorugh emulator.
Your link ===
http://www.danvillesignal.com/analog-devices-development-tools/sharc-blackfin-programmer.html
talks about the flash programming.
So can you please highlight on Booting of DSP through FLASH and where
exactly could I find the starting for the BOOT?
And as i have mentioned earlier, in the kit there is a decoder, Y0 of
which goes to Chip Select of Flash, which means @ booting DSP is supposed
to make some adresses out on the Address Bus.
Please clarify this.
>Al Clark wrote:
>
> ...
>
>> BTW, We are releasing a SHARC/Blackfin flsah programmer very soon. Here
Al,
Your email software wraps long lines. Mine wraps only at spaces. Here's
the link entire:
http://www.danvillesignal.com/analog-devices-development-tools/sharc-blackfin-programmer.html
Jerry
--
Engineering is the art of making what you want from things you can get.
�����������������������������������������������������������������������
Reply by Al Clark●February 1, 20082008-02-01
"patki.onkar" <patki.onkar@mte-india.com> wrote in
news:geSdnbdwtp9WhD7anZ2dnUVZ_j2dnZ2d@giganews.com:
> Hi all,
>
> I am referring to the schematic of "ADSP-21262 EZ-KIT Lite Evaluation
> Kit".
> In the memory part of schematic of this board, chip select to the
> memory (1M*8 Flash)is driven through the decoder(3 MSB of address
> lines in 8 bit data mode are input to the decoder).
> This means, for boot loading DSP Processor will generate addresses
> along with ALE and RD. This address will be in address range so that
> memory gets chip select through decoder.
>
> Now when powered up there is no program in DSP processor, then how
> this addresses and ALE are degenerated?
There is an internal bootloader in the 21262 internal ROM. It is executed
when the BMODE pins are set for parallel flash
>
> In the evaluation board, Y0 op of decoder goes to chip select of
> parallel flash memory. This means the particular address range of DSP
> address is for booting.
The boot program starts at the lowest address. You can see this by noting
that the decoder CS uses A23-A21 = 000
>
> But in the datasheet of ADSP-21262 I could not find boot address range
> ?
>
> Can you please clarify on the issue?
>
>
>
You can also use serial flash. We use this on our boards. It saves a lot
of board space. Thee is really no great benefit to the parallel flash
solution.
BTW, We are releasing a SHARC/Blackfin flsah programmer very soon. Here
is a link:
http://www.danvillesignal.com/analog-devices-development-tools/sharc-
blackfin-programmer.html
Al Clark
Danville Signal Processing, Inc.
Reply by patki.onkar●February 1, 20082008-02-01
Hi all,
I am referring to the schematic of "ADSP-21262 EZ-KIT Lite Evaluation
Kit".
In the memory part of schematic of this board, chip select to the memory
(1M*8 Flash)is driven through the decoder(3 MSB of address lines in 8 bit
data mode are input to the decoder).
This means, for boot loading DSP Processor will generate addresses along
with ALE and RD. This address will be in address range so that memory gets
chip select through decoder.
Now when powered up there is no program in DSP processor, then how this
addresses and ALE are degenerated?
In the evaluation board, Y0 op of decoder goes to chip select of parallel
flash memory. This means the particular address range of DSP address is
for booting.
But in the datasheet of ADSP-21262 I could not find boot address range ?
Can you please clarify on the issue?