Just wondering about a design I recently saw which had a DM642 interfaced to SDRAM using a 32-bit wide data bus. The SDRAM chip only has a 32-bit wide bus and the other 32 bits of the DM642 are not used. Not sure why it was designed this way as it only going to slow down the EMIF that much more. Can this design work? Is this going to be problem? Any special commands required on the DM642 to support this configuration? TIA Start a New Thread