Summary

This blog shows how to use a digital phase-locked loop (DPLL) to lock a numerically-controlled oscillator to a GPS 1PPS time reference. It walks through the DPLL components—phase detector, loop filter, NCO—plus practical tuning, jitter analysis, and embedded implementation tips so the reader can build a robust real-time timebase.

Key Takeaways

• Implement a DPLL architecture that synchronizes an NCO to a 1PPS input using a suitable phase detector and digital loop filter.
• Derive and set loop-filter (PI/second-order) coefficients to obtain the desired bandwidth, stability, and transient response.
• Tune the phase detector and NCO resolution to minimize cycle jitter and quantization-induced phase error.
• Evaluate timekeeping performance with phase error metrics and Allan deviation and mitigate noise sources.
• Mitigate embedded issues such as interrupt latency and fixed-point quantization via buffering, interpolation, and latency compensation.

Who Should Read This

Intermediate embedded DSP or communications engineers who need to synchronize a digital oscillator to a GNSS 1PPS reference for timekeeping, coherent sampling, or communications systems.

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