Summary

This report recounts the Google Summer of Code 2018 project to develop digital filter blocks in MyHDL and integrate them into the pyFDA toolchain. It explains the design, fixed-point considerations, HDL generation, and verification steps so readers learn how to move filter designs from pyFDA prototypes to synthesizable MyHDL blocks.

Key Takeaways

• Understand how to model common digital filters in MyHDL for synthesis and simulation.
• Implement fixed-point arithmetic and coefficient quantization suitable for FPGA/HDL targets.
• Generate synthesizable HDL from MyHDL and integrate those blocks into the pyFDA workflow.
• Validate filter behavior with testbenches and simulation to ensure parity with pyFDA designs.

Who Should Read This

DSP engineers, FPGA/HDL developers, or graduate students with some filter-design experience who want to automate conversion of pyFDA designs into synthesizable MyHDL/HDL blocks for real-time deployment.

Still RelevantIntermediate

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