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Dear friend, at present i am working with 10 SHARC(ADSP-21062) processors for a project involves multiprocessor environment .i have booted the 10 SHARC processor through link ports.but when i configuring my slave processors to transmit a character i am getting more interrupts to the Root processor which the root processor is not able to respond immediately.the processor hangs.i have also enabled the BUS Hang bit . please let me know how to get interrupts from individual processor though they are connected in tandem. i restrict my interrupts from all the processors through their ID pins but then too the processor hangs regards satish kumar. india |
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WORKING IN 10 sharc BOARD
Started by ●July 8, 2003
Reply by ●July 8, 20032003-07-08
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On Tue, 8 Jul 2003, satkumar_99 wrote: > at present i am working with 10 SHARC(ADSP-21062) processors for a > project involves multiprocessor environment .i have booted the 10 > SHARC processor through link ports.but when i configuring my slave > processors to transmit a character i am getting more interrupts to > the Root processor which the root processor is not able to respond > immediately.the processor hangs.i have also enabled the BUS Hang bit . Sounds like a fun toy you have there! You might need to put in an interrupt priority encoder and let some external hardware buffer all the interrupts. Then you'll have only 1 interrupt at at time to the main processor, and it can deal with each other processor in turn. > please let me know how to get interrupts from individual processor > though they are connected in tandem. > > i restrict my interrupts from all the processors through their ID > pins but then too the processor hangs Another possibility is to use the internal memory map and let the main processor read some of the shared ram of other processors. You are only allowed 6 processors in this configuration tho, so with 10 you will have to have some with the same id's and some way to switch between them. I think if they are all on the same bus, you need to make sure that only 6 with different id's can be on that bus at one time, and tri-state the others. Another way is to put them all in their own address space and allow them to write to a priority encoder for the main processor so it can then read each processors internal ram directly. Yet another way would be the dma engine in each processor - just move data into the main processor to tell it what that processor is doing. In any case, bus arbitration will be non-trivial! You may want some dual-ported ram inbetween all the processors so they are actually on their own bus all the time. Things can then run a lot faster. Patience, persistence, truth, Dr. mike |
