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hi! i am trying to use interface a 21065L to some external device that is slower than the DSP chip. i was wondering what i could to to keep the signals on the address and data bus active for a longer amount of time. could i just put nop's after the data write instruction or do i still have to change some settings? thanks!! carlo. |
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slower peripherals
Started by ●September 12, 2003
Reply by ●September 12, 20032003-09-12
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On Fri, 12 Sep 2003, lomaguindo wrote: > i am trying to use interface a 21065L to some external device > that is slower than the DSP chip. i was wondering what i could to to > keep the signals on the address and data bus active for a longer > amount of time. could i just put nop's after the data write > instruction or do i still have to change some settings? Use the RDY signal and set your external bus control to wait for it. The bus is asyncronous, you can wait as long as you like (but you need to turn of internal wait for that to work). Nop's won't work, but multiple accesses might. Patience, persistence, truth, Dr. mike |
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Reply by ●September 12, 20032003-09-12
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--On Friday, September 12, 2003 10:27 AM -0700 Mike Rosing <> wrote: > Use the RDY signal and set your external bus control to wait for > it. The bus is asyncronous, you can wait as long as you like (but > you need to turn of internal wait for that to work). One way to do this is to build a shift register clocked by the SHARC clock. The chip select for your device holds the shift register in reset when the device is not selected. Shift a one into the end, and the other end is wired to the RDY signal. Use as many taps as you need wait states. The same shift register can be used for multiple devices with different timing by using different taps for the RDY signal (OR'ing them to create the actual RDY) and qualifying each tap by that device's chip select. |
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Reply by ●September 12, 20032003-09-12
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I am using VisualDsp++ version 3.0 with service pack 1. When producing loader file with SPI 32 bit hostwidth, I got two lines which are very weired: See the following line 6,7. Anybody has this problem? 0x40bfb05b 0x40bf8345 0x00000002 0x0c000000 0x00000005 0x00000x00000000 0x00000x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000b3e 0x00000000 0x00000000 0x00000000 Thanks! hh_ca __________________________________ |
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Reply by ●September 13, 20032003-09-13
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I've got a question concerning the topic: is it possible to use the external bus in this fashion (with a slow external peripheral, communications paced by RDY signal) still using DMA in the DSP side??? JaaC --- Mike Rosing <> wrote: > On Fri, 12 Sep 2003, lomaguindo wrote: > > > i am trying to use interface a 21065L to some > external device > > that is slower than the DSP chip. i was wondering > what i could to to > > keep the signals on the address and data bus > active for a longer > > amount of time. could i just put nop's after the > data write > > instruction or do i still have to change some > settings? > > Use the RDY signal and set your external bus control > to wait for > it. The bus is asyncronous, you can wait as long as > you like (but > you need to turn of internal wait for that to work). > Nop's won't > work, but multiple accesses might. > > Patience, persistence, truth, > Dr. mike > > _____________________________________ > Note: If you do a simple "reply" with your email > client, only the author of this message will receive > your answer. You need to do a "reply all" if you > want your answer to be distributed to the entire > group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > To Post: Send an email to > > To Leave: Send an email to > Archives: http://groups.yahoo.com/group/adsp > > Other Groups: http://www.dsprelated.com/groups.php3 > ">http://docs.yahoo.com/info/terms/ __________________________________ |
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Reply by ●September 13, 20032003-09-13
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--On Friday, September 12, 2003 7:12 PM -0700 Jaime Andres Aranguren
Cardona <> wrote: > I've got a question concerning the topic: is it > possible to use the external bus in this fashion (with > a slow external peripheral, communications paced by > RDY signal) still using DMA in the DSP side??? The bus controller (which interprets the RDY signal) is independent of the DMA controller. The DMA controller submits a request to the bus controller to read/write an external word, and the bus controller then does the actual transaction. This is similar to DMA to SDRAM, which is paced by the SDRAM controller. |
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Reply by ●September 13, 20032003-09-13
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On Fri, 12 Sep 2003, Kenneth Porter wrote: > --On Friday, September 12, 2003 7:12 PM -0700 Jaime Andres Aranguren Cardona > <> wrote: > > > I've got a question concerning the topic: is it > > possible to use the external bus in this fashion (with > > a slow external peripheral, communications paced by > > RDY signal) still using DMA in the DSP side??? > > The bus controller (which interprets the RDY signal) is independent of the DMA > controller. The DMA controller submits a request to the bus controller to > read/write an external word, and the bus controller then does the actual > transaction. > > This is similar to DMA to SDRAM, which is paced by the SDRAM controller. Jaime, the answer is yes :-) Ken, that's a slick way to set up RDY. I've had some dma problems with a locked up bus and that seems like a way to slow the process down so I can make things more robust. Thanks! Patience, persistence, truth, Dr. mike |
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Reply by ●September 13, 20032003-09-13
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--On Friday, September 12, 2003 8:41 PM -0700 Mike Rosing <> wrote: > Ken, that's a slick way to set up RDY. I learned it back in the early 80's from an old master (Stu Nelson) who designed Z80 and 68000 boards. (His real baby was a clone of the DEC PDP-10, using bit-slice chips.) We used that kind of scheme to create a DRAM controller out of discrete TTL, triggering RAS, CAS, and the address mux from taps from a shift register triggered from the 68000's address strobe signal. Nowadays you can easily do this in a small FPGA. Just get some grid paper and treat each grid square as a half-clock cycle. Draw the clock across the paper, then draw what your waveforms should look like underneath. Then design a shift register to generate the waveforms. You can combine taps with AND/OR/XOR to generate pulses of varying characteristics in the middle of your cycle. |
Reply by ●September 14, 20032003-09-14
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Thanks for your response, Mike. JaaC --- Mike Rosing <> wrote: > On Fri, 12 Sep 2003, Kenneth Porter wrote: > > > --On Friday, September 12, 2003 7:12 PM -0700 > Jaime Andres Aranguren Cardona > > <> wrote: > > > > > I've got a question concerning the topic: is it > > > possible to use the external bus in this fashion > (with > > > a slow external peripheral, communications paced > by > > > RDY signal) still using DMA in the DSP side??? > > > > The bus controller (which interprets the RDY > signal) is independent of the DMA > > controller. The DMA controller submits a request > to the bus controller to > > read/write an external word, and the bus > controller then does the actual > > transaction. > > > > This is similar to DMA to SDRAM, which is paced by > the SDRAM controller. > > Jaime, the answer is yes :-) > > Ken, that's a slick way to set up RDY. I've had > some dma problems with a > locked up bus and that seems like a way to slow the > process down so I can > make things more robust. Thanks! > > Patience, persistence, truth, > Dr. mike > > _____________________________________ > Note: If you do a simple "reply" with your email > client, only the author of this message will receive > your answer. You need to do a "reply all" if you > want your answer to be distributed to the entire > group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > To Post: Send an email to > > To Leave: Send an email to > Archives: http://groups.yahoo.com/group/adsp > > Other Groups: http://www.dsprelated.com/groups.php3 > ">http://docs.yahoo.com/info/terms/ __________________________________ |
Reply by ●September 14, 20032003-09-14
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I just found out that those two lines are the two variables at address 0x0c000000 and 0x0c000001. These are external memory addresses. There was a warning during the project building process saying external memory using 32 bits (or something to that effect). This is definitely something new in versin 3.0. hh_ca --- h h <> wrote: > I am using VisualDsp++ version 3.0 with service pack > 1. When producing loader file with SPI 32 bit > hostwidth, I got two lines which are very weired: > See > the following line 6,7. Anybody has this problem? > 0x40bfb05b > 0x40bf8345 > 0x00000002 > 0x0c000000 > 0x00000005 > 0x00000x00000000 > 0x00000x00000000 > 0x00000000 > 0x00000000 > 0x00000000 > 0x00000000 > 0x00000b3e > 0x00000000 > 0x00000000 > 0x00000000 > > Thanks! > > hh_ca > > __________________________________ > _____________________________________ > Note: If you do a simple "reply" with your email > client, only the author of this message will receive > your answer. You need to do a "reply all" if you > want your answer to be distributed to the entire > group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > To Post: Send an email to > > To Leave: Send an email to > Archives: http://groups.yahoo.com/group/adsp > > Other Groups: http://www.dsprelated.com/groups.php3 > ">http://docs.yahoo.com/info/terms/ __________________________________ |
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