I'm having some problems with a Host Bus interface between a Coldfire
and a ADSP-21161N processor. If I reset the Coldfire and DSP and
wirte to the MSGR register of the DSP, if I do it manually, it seems
that I can write and read without a problem. When I try to write and
read within a program The DSP locks up soon after starting, but not
at the same place. What happens that is different from a successful
write is that CS and HBR go low and REDY from the DSP goes low and
that is where it hangs. I never get HBG so I never get REDY going
high which I am using as a TA signal to the Coldfire, so the Coldfire
eventually times out with a bus fault. This occurs after a LONG
delay >1uSec.
Any ideas why the HBG never comes? Has anyone else seen this
sequence? We are using the same interface we used on the Host Bus of
our 21065 project and it seemed to work fine. I've checked our
schematic against the interface in the ADSP-21161 Hardware Ref and it
is identical.
Thanks for your help.
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
Host Bus Problem.
Started by ●May 5, 2005
Reply by ●May 5, 20052005-05-05
On Thu, 5 May 2005, Steve Holle wrote:
> I'm having some problems with a Host Bus interface between a Coldfire
> and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> wirte to the MSGR register of the DSP, if I do it manually, it seems
> that I can write and read without a problem. When I try to write and
> read within a program The DSP locks up soon after starting, but not
> at the same place. What happens that is different from a successful
> write is that CS and HBR go low and REDY from the DSP goes low and
> that is where it hangs. I never get HBG so I never get REDY going
> high which I am using as a TA signal to the Coldfire, so the Coldfire
> eventually times out with a bus fault. This occurs after a LONG
> delay >1uSec.
>
> Any ideas why the HBG never comes? Has anyone else seen this
> sequence? We are using the same interface we used on the Host Bus of
> our 21065 project and it seemed to work fine. I've checked our
> schematic against the interface in the ADSP-21161 Hardware Ref and it
> is identical.
No, but I've had problems with DMA locking up at weird times. Check
your timing and noise levels. The SHARC's are fairly picky (which means
they can see glitches) so you need clean signals. The 065 is not as fast
as the 161, so I'd suspect setup and hold times as well as glitching.
Good luck, it ain't gonna be easy to find.
Patience, persistence, truth,
Dr. mike
> I'm having some problems with a Host Bus interface between a Coldfire
> and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> wirte to the MSGR register of the DSP, if I do it manually, it seems
> that I can write and read without a problem. When I try to write and
> read within a program The DSP locks up soon after starting, but not
> at the same place. What happens that is different from a successful
> write is that CS and HBR go low and REDY from the DSP goes low and
> that is where it hangs. I never get HBG so I never get REDY going
> high which I am using as a TA signal to the Coldfire, so the Coldfire
> eventually times out with a bus fault. This occurs after a LONG
> delay >1uSec.
>
> Any ideas why the HBG never comes? Has anyone else seen this
> sequence? We are using the same interface we used on the Host Bus of
> our 21065 project and it seemed to work fine. I've checked our
> schematic against the interface in the ADSP-21161 Hardware Ref and it
> is identical.
No, but I've had problems with DMA locking up at weird times. Check
your timing and noise levels. The SHARC's are fairly picky (which means
they can see glitches) so you need clean signals. The 065 is not as fast
as the 161, so I'd suspect setup and hold times as well as glitching.
Good luck, it ain't gonna be easy to find.
Patience, persistence, truth,
Dr. mike
Reply by ●May 5, 20052005-05-05
Some additional info. The failure only occurs during writes, I can
read continuously with no problem. Also, after the crash, the Slave
Write FIFO Pending Data ( SWPD ) bit in the SYSTAT is set which seems
to indicate the DSP is aware that a Host Bus Write is pending. Interesting.
At 02:07 PM 5/5/2005, Mike Rosing wrote:
>On Thu, 5 May 2005, Steve Holle wrote:
>
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
>
>No, but I've had problems with DMA locking up at weird times. Check
>your timing and noise levels. The SHARC's are fairly picky (which means
>they can see glitches) so you need clean signals. The 065 is not as fast
>as the 161, so I'd suspect setup and hold times as well as glitching.
>
>Good luck, it ain't gonna be easy to find.
>
>Patience, persistence, truth,
>Dr. mike
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
read continuously with no problem. Also, after the crash, the Slave
Write FIFO Pending Data ( SWPD ) bit in the SYSTAT is set which seems
to indicate the DSP is aware that a Host Bus Write is pending. Interesting.
At 02:07 PM 5/5/2005, Mike Rosing wrote:
>On Thu, 5 May 2005, Steve Holle wrote:
>
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
>
>No, but I've had problems with DMA locking up at weird times. Check
>your timing and noise levels. The SHARC's are fairly picky (which means
>they can see glitches) so you need clean signals. The 065 is not as fast
>as the 161, so I'd suspect setup and hold times as well as glitching.
>
>Good luck, it ain't gonna be easy to find.
>
>Patience, persistence, truth,
>Dr. mike
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
Reply by ●May 6, 20052005-05-06
At 05:30 PM 5/5/2005, Jon Harris wrote:
>Can you clarify what you mean by write/read manually vs. within a program?
By manually, I mean via the monitor program (uMon) we have running on
the Coldfire.
>
>FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
>anything similar. Do you have more than one piece of hardware to try this on,
>and if so,
Unfortunately, No.
> is the behaviour consistent?
The board I have does have two independent and identical DSP's on it
connected to different decoded chip selects and both act
similarly. The failure ONLY occurs with writes, I've since found
out, and when it locks the SWPD is set in the SYSTAT register when it
hangs indicating the DSP knows it's in slave write mode but doesn't
generate HBG. Also, the number of writes to a crash is
indeterminate, sometimes 1, other times between 10 to 15.
Any help you could give would be greatly appreciated. >--- Steve Holle <sholle@shol...> wrote:
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
> >
> > Thanks for your help.
> >
> > Steve Holle
> > Link Communications, Inc.
> > 1035 Cerise Rd.
> > Billings, MT 59101
> > sholle@shol...
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>__________________________________
>
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
>Can you clarify what you mean by write/read manually vs. within a program?
By manually, I mean via the monitor program (uMon) we have running on
the Coldfire.
>
>FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
>anything similar. Do you have more than one piece of hardware to try this on,
>and if so,
Unfortunately, No.
> is the behaviour consistent?
The board I have does have two independent and identical DSP's on it
connected to different decoded chip selects and both act
similarly. The failure ONLY occurs with writes, I've since found
out, and when it locks the SWPD is set in the SYSTAT register when it
hangs indicating the DSP knows it's in slave write mode but doesn't
generate HBG. Also, the number of writes to a crash is
indeterminate, sometimes 1, other times between 10 to 15.
Any help you could give would be greatly appreciated. >--- Steve Holle <sholle@shol...> wrote:
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
> >
> > Thanks for your help.
> >
> > Steve Holle
> > Link Communications, Inc.
> > 1035 Cerise Rd.
> > Billings, MT 59101
> > sholle@shol...
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>__________________________________
>
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
Reply by ●May 6, 20052005-05-06
Also, could you let me know how you have your Coldfire chip select
set up for the DSP?
Thanks.
At 05:30 PM 5/5/2005, Jon Harris wrote:
>Can you clarify what you mean by write/read manually vs. within a program?
By manually, I mean via the monitor program (uMon) we have running on
the Coldfire.
>
>FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
>anything similar. Do you have more than one piece of hardware to try this on,
>and if so,
Unfortunately, No.
> is the behaviour consistent?
The board I have does have two independent and identical DSP's on it
connected to different decoded chip selects and both act
similarly. The failure ONLY occurs with writes, I've since found
out, and when it locks the SWPD is set in the SYSTAT register when it
hangs indicating the DSP knows it's in slave write mode but doesn't
generate HBG. Also, the number of writes to a crash is
indeterminate, sometimes 1, other times between 10 to 15.
Any help you could give would be greatly appreciated. >--- Steve Holle <sholle@shol...> wrote:
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
> >
> > Thanks for your help.
> >
> > Steve Holle
> > Link Communications, Inc.
> > 1035 Cerise Rd.
> > Billings, MT 59101
> > sholle@shol...
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>__________________________________
>
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
set up for the DSP?
Thanks.
At 05:30 PM 5/5/2005, Jon Harris wrote:
>Can you clarify what you mean by write/read manually vs. within a program?
By manually, I mean via the monitor program (uMon) we have running on
the Coldfire.
>
>FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
>anything similar. Do you have more than one piece of hardware to try this on,
>and if so,
Unfortunately, No.
> is the behaviour consistent?
The board I have does have two independent and identical DSP's on it
connected to different decoded chip selects and both act
similarly. The failure ONLY occurs with writes, I've since found
out, and when it locks the SWPD is set in the SYSTAT register when it
hangs indicating the DSP knows it's in slave write mode but doesn't
generate HBG. Also, the number of writes to a crash is
indeterminate, sometimes 1, other times between 10 to 15.
Any help you could give would be greatly appreciated. >--- Steve Holle <sholle@shol...> wrote:
> > I'm having some problems with a Host Bus interface between a Coldfire
> > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > wirte to the MSGR register of the DSP, if I do it manually, it seems
> > that I can write and read without a problem. When I try to write and
> > read within a program The DSP locks up soon after starting, but not
> > at the same place. What happens that is different from a successful
> > write is that CS and HBR go low and REDY from the DSP goes low and
> > that is where it hangs. I never get HBG so I never get REDY going
> > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > eventually times out with a bus fault. This occurs after a LONG
> > delay >1uSec.
> >
> > Any ideas why the HBG never comes? Has anyone else seen this
> > sequence? We are using the same interface we used on the Host Bus of
> > our 21065 project and it seemed to work fine. I've checked our
> > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > is identical.
> >
> > Thanks for your help.
> >
> > Steve Holle
> > Link Communications, Inc.
> > 1035 Cerise Rd.
> > Billings, MT 59101
> > sholle@shol...
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
>__________________________________
>
Steve Holle
Link Communications, Inc.
1035 Cerise Rd.
Billings, MT 59101
sholle@shol...
Reply by ●May 6, 20052005-05-06
Hello
I need to modify SPI speed when booting via SPI. Default value is
200kHz, and I want to increase it . does anybody try this configuration
or has an idea on how to proceed?
Help would be greatly appreciated
Thank's in advance
Best regards
Stephane
I need to modify SPI speed when booting via SPI. Default value is
200kHz, and I want to increase it . does anybody try this configuration
or has an idea on how to proceed?
Help would be greatly appreciated
Thank's in advance
Best regards
Stephane
Reply by ●May 7, 20052005-05-07
Hi
You can configure the SPI SCLK in a initialization block (see EE-240, in
www.analog.com). This block is loaded in internal RAM and executed,
before others blocks. So those blocks will be loaded more fast.
cya
Samuel Vale
Em S, 2005-05-07 01:07 +0200, Sthane GOUEL - Arbos Technology
escreveu:
> Hello
>
> I need to modify SPI speed when booting via SPI. Default value is
> 200kHz, and I want to increase it . does anybody try this configuration
> or has an idea on how to proceed?
>
> Help would be greatly appreciated
>
> Thank's in advance
>
> Best regards
>
> Stephane
>
--
Samuel Vale
You can configure the SPI SCLK in a initialization block (see EE-240, in
www.analog.com). This block is loaded in internal RAM and executed,
before others blocks. So those blocks will be loaded more fast.
cya
Samuel Vale
Em S, 2005-05-07 01:07 +0200, Sthane GOUEL - Arbos Technology
escreveu:
> Hello
>
> I need to modify SPI speed when booting via SPI. Default value is
> 200kHz, and I want to increase it . does anybody try this configuration
> or has an idea on how to proceed?
>
> Help would be greatly appreciated
>
> Thank's in advance
>
> Best regards
>
> Stephane
>
--
Samuel Vale
Reply by ●May 9, 20052005-05-09
Hi,
I've check EE240, but I dont see where you can modify SPICLK. In
initialisation block, i'm just able to modify PF who will be use as CS
pin. I'm working in SPI master mode (BMODE == 11) with an E2P.
Is it correct , or i miss something?
Thank's in advance
-----Message d'origine-----
De: adsp@adsp... [mailto:adsp@adsp...] De la part de
Phractal
Envoy samedi 7 mai 2005 18:16
: adsp@adsp...
Objet: Re: [adsp] BF533 : Booting via SPI at specific speed
Hi
You can configure the SPI SCLK in a initialization block (see EE-240, in
www.analog.com). This block is loaded in internal RAM and executed,
before others blocks. So those blocks will be loaded more fast.
cya
Samuel Vale
Em S, 2005-05-07 01:07 +0200, Sthane GOUEL - Arbos Technology
escreveu:
> Hello
>
> I need to modify SPI speed when booting via SPI. Default value is
> 200kHz, and I want to increase it . does anybody try this
configuration
> or has an idea on how to proceed?
>
> Help would be greatly appreciated
>
> Thank's in advance
>
> Best regards
>
> Stephane
>
--
Samuel Vale
Reply by ●May 9, 20052005-05-09
--- Steve Holle <sholle@shol...> wrote:
> Also, could you let me know how you have your Coldfire chip select
> set up for the DSP?
> Thanks.
My system also has an FPGA, which acts as an intermediary between the CF and
DSP. So the FPGA actually generates all the chip select/read/write signals for
the DSP. Probably doesn't help you much, I'm afraid.
> At 05:30 PM 5/5/2005, Jon Harris wrote:
> >Can you clarify what you mean by write/read manually vs. within a program?
>
> By manually, I mean via the monitor program (uMon) we have running on
> the Coldfire.
OK, understood. I don't have a monitor program, so again I can't directly
relate.
> >FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
> >anything similar. Do you have more than one piece of hardware to try this
> on,
> >and if so,
>
> Unfortunately, No.
That's a shame.
> > is the behavior consistent?
>
> The board I have does have two independent and identical DSP's on it
> connected to different decoded chip selects and both act
> similarly. The failure ONLY occurs with writes, I've since found
> out, and when it locks the SWPD is set in the SYSTAT register when it
> hangs indicating the DSP knows it's in slave write mode but doesn't
> generate HBG. Also, the number of writes to a crash is
> indeterminate, sometimes 1, other times between 10 to 15.
>
> Any help you could give would be greatly appreciated.
Sounds like a tough one. I don't have any great ideas for you, but I'll pass
along some general info. You really need to figure out first if this is a
hardware or software problem. And if it is hardware-related, is it a design
problem or a manufacturing problem? That is where a second board would be very
handy. Maybe you can come up with some more tests to try to figure out the
above info and isolate the problem further. The fact that it takes an
"indeterminate" number of writes to fail points toward hardware (assuming all
writes are to the same address) and possibly some marginal signal integrity?
Check clocks, power supply voltages, grounds, and look for any glitches on your
read/write/chip select lines.
Also, try to figure out what is different between a manual write and a
code-based write. Different wait states? Use an oscilloscope and see if you
can see any differences on any of the key lines.
> >--- Steve Holle <sholle@shol...> wrote:
> > > I'm having some problems with a Host Bus interface between a Coldfire
> > > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > > write to the MSGR register of the DSP, if I do it manually, it seems
> > > that I can write and read without a problem. When I try to write and
> > > read within a program The DSP locks up soon after starting, but not
> > > at the same place. What happens that is different from a successful
> > > write is that CS and HBR go low and REDY from the DSP goes low and
> > > that is where it hangs. I never get HBG so I never get REDY going
> > > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > > eventually times out with a bus fault. This occurs after a LONG
> > > delay >1uSec.
> > >
> > > Any ideas why the HBG never comes? Has anyone else seen this
> > > sequence? We are using the same interface we used on the Host Bus of
> > > our 21065 project and it seemed to work fine. I've checked our
> > > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > > is identical.
> > >
> > > Thanks for your help.
> > >
> > > Steve Holle
> > > Link Communications, Inc.
> > > 1035 Cerise Rd.
> > > Billings, MT 59101
> > > sholle@shol...
__________________________________________________
> Also, could you let me know how you have your Coldfire chip select
> set up for the DSP?
> Thanks.
My system also has an FPGA, which acts as an intermediary between the CF and
DSP. So the FPGA actually generates all the chip select/read/write signals for
the DSP. Probably doesn't help you much, I'm afraid.
> At 05:30 PM 5/5/2005, Jon Harris wrote:
> >Can you clarify what you mean by write/read manually vs. within a program?
>
> By manually, I mean via the monitor program (uMon) we have running on
> the Coldfire.
OK, understood. I don't have a monitor program, so again I can't directly
relate.
> >FWIW, I've worked on a project with ColdFire and 21161 and didn't notice
> >anything similar. Do you have more than one piece of hardware to try this
> on,
> >and if so,
>
> Unfortunately, No.
That's a shame.
> > is the behavior consistent?
>
> The board I have does have two independent and identical DSP's on it
> connected to different decoded chip selects and both act
> similarly. The failure ONLY occurs with writes, I've since found
> out, and when it locks the SWPD is set in the SYSTAT register when it
> hangs indicating the DSP knows it's in slave write mode but doesn't
> generate HBG. Also, the number of writes to a crash is
> indeterminate, sometimes 1, other times between 10 to 15.
>
> Any help you could give would be greatly appreciated.
Sounds like a tough one. I don't have any great ideas for you, but I'll pass
along some general info. You really need to figure out first if this is a
hardware or software problem. And if it is hardware-related, is it a design
problem or a manufacturing problem? That is where a second board would be very
handy. Maybe you can come up with some more tests to try to figure out the
above info and isolate the problem further. The fact that it takes an
"indeterminate" number of writes to fail points toward hardware (assuming all
writes are to the same address) and possibly some marginal signal integrity?
Check clocks, power supply voltages, grounds, and look for any glitches on your
read/write/chip select lines.
Also, try to figure out what is different between a manual write and a
code-based write. Different wait states? Use an oscilloscope and see if you
can see any differences on any of the key lines.
> >--- Steve Holle <sholle@shol...> wrote:
> > > I'm having some problems with a Host Bus interface between a Coldfire
> > > and a ADSP-21161N processor. If I reset the Coldfire and DSP and
> > > write to the MSGR register of the DSP, if I do it manually, it seems
> > > that I can write and read without a problem. When I try to write and
> > > read within a program The DSP locks up soon after starting, but not
> > > at the same place. What happens that is different from a successful
> > > write is that CS and HBR go low and REDY from the DSP goes low and
> > > that is where it hangs. I never get HBG so I never get REDY going
> > > high which I am using as a TA signal to the Coldfire, so the Coldfire
> > > eventually times out with a bus fault. This occurs after a LONG
> > > delay >1uSec.
> > >
> > > Any ideas why the HBG never comes? Has anyone else seen this
> > > sequence? We are using the same interface we used on the Host Bus of
> > > our 21065 project and it seemed to work fine. I've checked our
> > > schematic against the interface in the ADSP-21161 Hardware Ref and it
> > > is identical.
> > >
> > > Thanks for your help.
> > >
> > > Steve Holle
> > > Link Communications, Inc.
> > > 1035 Cerise Rd.
> > > Billings, MT 59101
> > > sholle@shol...
__________________________________________________
Reply by ●May 11, 20052005-05-11
Hello All,
I am
finding the Emedia based solution kit for Digital Home gateway
application.We want to use this product with Analog camera, with
integrating the available SDK for Linux platform. and Hardware MPEG-4
encoding.
Could you please
suggest me the specific evm kit supports to my application.
Regards,
Meenakshi
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