Hello everybody, I am interested in the analysis of
the assembly code generated by the VisualDSP++ 3.5
compiler for a Blackfin 533 ezkit lite platform.
However I'm not an expert so I would like to know if
there is some tutorial about this concern... for
example is there a fast way to understand if two
istruction are executed in parallel?
In TI CCS the parallel assembler instruction are
denoted with the symbol ||, is there something like
that also in ADI?
Thanks a lot Giovanni
How to understand assembler
Started by ●May 17, 2005
Reply by ●May 17, 20052005-05-17
On Tue, 17 May 2005, Giovanni Parodi wrote:
> Hello everybody, I am interested in the analysis of
> the assembly code generated by the VisualDSP++ 3.5
> compiler for a Blackfin 533 ezkit lite platform.
> However I'm not an expert so I would like to know if
> there is some tutorial about this concern... for
> example is there a fast way to understand if two
> istruction are executed in parallel?
> In TI CCS the parallel assembler instruction are
> denoted with the symbol ||, is there something like
> that also in ADI?
> Thanks a lot Giovanni
No, the ADI assembler puts many sub components for the same parallel
instruction on one line using "," as separator. So in a TI instruction
you might have
add r0,r1
|| mul r2,r3
in an ADI instruction you'd put
r0 = r0+r1, r2 = r2*r3
(in both cases that combination of registers won't actually work, but it
gives you the syntax).
I've used both, and I like the ADI syntax better because of the = sign.
but it doesn't matter, you get used it. Or like my grandfather used to
say "you get used to hanging if you hang long enough"
Patience, persistence, truth,
Dr. mike
> Hello everybody, I am interested in the analysis of
> the assembly code generated by the VisualDSP++ 3.5
> compiler for a Blackfin 533 ezkit lite platform.
> However I'm not an expert so I would like to know if
> there is some tutorial about this concern... for
> example is there a fast way to understand if two
> istruction are executed in parallel?
> In TI CCS the parallel assembler instruction are
> denoted with the symbol ||, is there something like
> that also in ADI?
> Thanks a lot Giovanni
No, the ADI assembler puts many sub components for the same parallel
instruction on one line using "," as separator. So in a TI instruction
you might have
add r0,r1
|| mul r2,r3
in an ADI instruction you'd put
r0 = r0+r1, r2 = r2*r3
(in both cases that combination of registers won't actually work, but it
gives you the syntax).
I've used both, and I like the ADI syntax better because of the = sign.
but it doesn't matter, you get used it. Or like my grandfather used to
say "you get used to hanging if you hang long enough"
Patience, persistence, truth,
Dr. mike
Reply by ●May 17, 20052005-05-17
--- Mike Rosing <eresrch@eres...> ha scritto:
> On Tue, 17 May 2005, Giovanni Parodi wrote:
>
> > Hello everybody, I am interested in the analysis
> of
> > the assembly code generated by the VisualDSP++ 3.5
> > compiler for a Blackfin 533 ezkit lite platform.
> > However I'm not an expert so I would like to know
> if
> > there is some tutorial about this concern... for
> > example is there a fast way to understand if two
> > istruction are executed in parallel?
> > In TI CCS the parallel assembler instruction are
> > denoted with the symbol ||, is there something
> like
> > that also in ADI?
> > Thanks a lot Giovanni
>
> No, the ADI assembler puts many sub components for
> the same parallel
> instruction on one line using "," as separator. So
> in a TI instruction
> you might have
>
> add r0,r1
> || mul r2,r3
>
> in an ADI instruction you'd put
>
> r0 = r0+r1, r2 = r2*r3
>
> (in both cases that combination of registers won't
> actually work, but it
> gives you the syntax).
>
> I've used both, and I like the ADI syntax better
> because of the = sign.
> but it doesn't matter, you get used it. Or like my
> grandfather used to
> say "you get used to hanging if you hang long
> enough"
>
> Patience, persistence, truth,
> Dr. mike >
> adsp-unsubscribe@adsp... Thanks a lot for your advice, however I have some
problem with the feedback provided by ADI compiler. In
fact for example in CCS there are tools that say you
how much is exploited your pipeline, how are balanced
the acces to the different functional units etc.
I didn-t find nothing like that in ADI, or better I
found the pipeline viewer that-s a very beautiful
tool, but that cannot be used if you use DMA becuse
the simulator seems not to support this hardware
specific aspect.
Thanks a lot Giovanni
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Reply by ●May 17, 20052005-05-17
On Tue, 17 May 2005, Giovanni Parodi wrote:
> Thanks a lot for your advice, however I have some
> problem with the feedback provided by ADI compiler. In
> fact for example in CCS there are tools that say you
> how much is exploited your pipeline, how are balanced
> the acces to the different functional units etc.
> I didn-t find nothing like that in ADI, or better I
> found the pipeline viewer that-s a very beautiful
> tool, but that cannot be used if you use DMA becuse
> the simulator seems not to support this hardware
> specific aspect.
> Thanks a lot Giovanni
the blackfin's pipeline is not so sophisticated as the SHARC's,
nor as complicated as some TI parts. I would hope that the
tool that helps tell you how well the pipeline is full could
also tell the compiler how to optimize things better. At present
this is a state of the art challenge.
I think the VDSP comes with a profiling tool so you can see how many clock
cycles you spend in any one location. That may help point you to places
that need further optimization, but it won't necessarily tell you how full
your pipes are.
Patience, persistence, truth,
Dr. mike
> Thanks a lot for your advice, however I have some
> problem with the feedback provided by ADI compiler. In
> fact for example in CCS there are tools that say you
> how much is exploited your pipeline, how are balanced
> the acces to the different functional units etc.
> I didn-t find nothing like that in ADI, or better I
> found the pipeline viewer that-s a very beautiful
> tool, but that cannot be used if you use DMA becuse
> the simulator seems not to support this hardware
> specific aspect.
> Thanks a lot Giovanni
the blackfin's pipeline is not so sophisticated as the SHARC's,
nor as complicated as some TI parts. I would hope that the
tool that helps tell you how well the pipeline is full could
also tell the compiler how to optimize things better. At present
this is a state of the art challenge.
I think the VDSP comes with a profiling tool so you can see how many clock
cycles you spend in any one location. That may help point you to places
that need further optimization, but it won't necessarily tell you how full
your pipes are.
Patience, persistence, truth,
Dr. mike
Reply by ●May 18, 20052005-05-18
--- Mike Rosing <eresrch@eres...> ha scritto:
> On Tue, 17 May 2005, Giovanni Parodi wrote:
>
> > Thanks a lot for your advice, however I have some
> > problem with the feedback provided by ADI
> compiler. In
> > fact for example in CCS there are tools that say
> you
> > how much is exploited your pipeline, how are
> balanced
> > the acces to the different functional units etc.
> > I didn-t find nothing like that in ADI, or better
> I
> > found the pipeline viewer that-s a very beautiful
> > tool, but that cannot be used if you use DMA
> becuse
> > the simulator seems not to support this hardware
> > specific aspect.
> > Thanks a lot Giovanni
>
> the blackfin's pipeline is not so sophisticated as
> the SHARC's,
> nor as complicated as some TI parts. I would hope
> that the
> tool that helps tell you how well the pipeline is
> full could
> also tell the compiler how to optimize things
> better. At present
> this is a state of the art challenge.
>
> I think the VDSP comes with a profiling tool so you
> can see how many clock
> cycles you spend in any one location. That may help
> point you to places
> that need further optimization, but it won't
> necessarily tell you how full
> your pipes are.
>
> Patience, persistence, truth,
> Dr. mike
Thanks a lot for your advice
Giovanni
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Reply by ●May 18, 20052005-05-18
Giovanni,
Try to read on PGO (Profile Guided Optimization). As I
undertand it, it is a means to gather information at
runtime from the execution of the program, which can
be used to help the compiler to produce more efficient
code. regarding this topic, I'd expect to exist some
documntation on your original question: "How to
understand assembler", or better said, "how to
understand what the compiler did to produce that
assembly code". Another question, is "how to
understand how good is the assembler code produced y
the compiler"
Rgards,
JaaC
--- Mike Rosing <eresrch@eres...> wrote:
> On Tue, 17 May 2005, Giovanni Parodi wrote:
>
> > Thanks a lot for your advice, however I have some
> > problem with the feedback provided by ADI
> compiler. In
> > fact for example in CCS there are tools that say
> you
> > how much is exploited your pipeline, how are
> balanced
> > the acces to the different functional units etc.
> > I didn-t find nothing like that in ADI, or better
> I
> > found the pipeline viewer that-s a very beautiful
> > tool, but that cannot be used if you use DMA
> becuse
> > the simulator seems not to support this hardware
> > specific aspect.
> > Thanks a lot Giovanni
>
> the blackfin's pipeline is not so sophisticated as
> the SHARC's,
> nor as complicated as some TI parts. I would hope
> that the
> tool that helps tell you how well the pipeline is
> full could
> also tell the compiler how to optimize things
> better. At present
> this is a state of the art challenge.
>
> I think the VDSP comes with a profiling tool so you
> can see how many clock
> cycles you spend in any one location. That may help
> point you to places
> that need further optimization, but it won't
> necessarily tell you how full
> your pipes are.
>
> Patience, persistence, truth,
> Dr. mike
Jaime Andr Aranguren Cardona
jaime.aranguren@jaim...
jaime.aranguren@jaim...
__________________________________
Try to read on PGO (Profile Guided Optimization). As I
undertand it, it is a means to gather information at
runtime from the execution of the program, which can
be used to help the compiler to produce more efficient
code. regarding this topic, I'd expect to exist some
documntation on your original question: "How to
understand assembler", or better said, "how to
understand what the compiler did to produce that
assembly code". Another question, is "how to
understand how good is the assembler code produced y
the compiler"
Rgards,
JaaC
--- Mike Rosing <eresrch@eres...> wrote:
> On Tue, 17 May 2005, Giovanni Parodi wrote:
>
> > Thanks a lot for your advice, however I have some
> > problem with the feedback provided by ADI
> compiler. In
> > fact for example in CCS there are tools that say
> you
> > how much is exploited your pipeline, how are
> balanced
> > the acces to the different functional units etc.
> > I didn-t find nothing like that in ADI, or better
> I
> > found the pipeline viewer that-s a very beautiful
> > tool, but that cannot be used if you use DMA
> becuse
> > the simulator seems not to support this hardware
> > specific aspect.
> > Thanks a lot Giovanni
>
> the blackfin's pipeline is not so sophisticated as
> the SHARC's,
> nor as complicated as some TI parts. I would hope
> that the
> tool that helps tell you how well the pipeline is
> full could
> also tell the compiler how to optimize things
> better. At present
> this is a state of the art challenge.
>
> I think the VDSP comes with a profiling tool so you
> can see how many clock
> cycles you spend in any one location. That may help
> point you to places
> that need further optimization, but it won't
> necessarily tell you how full
> your pipes are.
>
> Patience, persistence, truth,
> Dr. mike
Jaime Andr Aranguren Cardona
jaime.aranguren@jaim...
jaime.aranguren@jaim...
__________________________________
Reply by ●May 18, 20052005-05-18
Thanks a lot for your idea, I didn't know this tool,
now I will read the documentation provided from ADI.
Thanks again for your hint.
Talking about the other question that I posted in fact
you re right, my question should be "how to understand
how good is the assembler code produced by the
compiler", but my english is not so good..
Thanks again
Giovanni --- Jaime Andres Aranguren Cardona
<jaime_aranguren@jaim...> ha scritto:
> Giovanni,
>
> Try to read on PGO (Profile Guided Optimization). As
> I
> undertand it, it is a means to gather information at
> runtime from the execution of the program, which can
> be used to help the compiler to produce more
> efficient
> code. regarding this topic, I'd expect to exist some
> documntation on your original question: "How to
> understand assembler", or better said, "how to
> understand what the compiler did to produce that
> assembly code". Another question, is "how to
> understand how good is the assembler code produced y
> the compiler"
>
> Rgards,
>
> JaaC
>
> --- Mike Rosing <eresrch@eres...> wrote:
> > On Tue, 17 May 2005, Giovanni Parodi wrote:
> >
> > > Thanks a lot for your advice, however I have
> some
> > > problem with the feedback provided by ADI
> > compiler. In
> > > fact for example in CCS there are tools that say
> > you
> > > how much is exploited your pipeline, how are
> > balanced
> > > the acces to the different functional units etc.
> > > I didn-t find nothing like that in ADI, or
> better
> > I
> > > found the pipeline viewer that-s a very
> beautiful
> > > tool, but that cannot be used if you use DMA
> > becuse
> > > the simulator seems not to support this hardware
> > > specific aspect.
> > > Thanks a lot Giovanni
> >
> > the blackfin's pipeline is not so sophisticated as
> > the SHARC's,
> > nor as complicated as some TI parts. I would hope
> > that the
> > tool that helps tell you how well the pipeline is
> > full could
> > also tell the compiler how to optimize things
> > better. At present
> > this is a state of the art challenge.
> >
> > I think the VDSP comes with a profiling tool so
> you
> > can see how many clock
> > cycles you spend in any one location. That may
> help
> > point you to places
> > that need further optimization, but it won't
> > necessarily tell you how full
> > your pipes are.
> >
> > Patience, persistence, truth,
> > Dr. mike > Jaime Andr Aranguren Cardona
> jaime.aranguren@jaim...
> jaime.aranguren@jaim... >
>
> __________________________________
>
>
___________________________________
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now I will read the documentation provided from ADI.
Thanks again for your hint.
Talking about the other question that I posted in fact
you re right, my question should be "how to understand
how good is the assembler code produced by the
compiler", but my english is not so good..
Thanks again
Giovanni --- Jaime Andres Aranguren Cardona
<jaime_aranguren@jaim...> ha scritto:
> Giovanni,
>
> Try to read on PGO (Profile Guided Optimization). As
> I
> undertand it, it is a means to gather information at
> runtime from the execution of the program, which can
> be used to help the compiler to produce more
> efficient
> code. regarding this topic, I'd expect to exist some
> documntation on your original question: "How to
> understand assembler", or better said, "how to
> understand what the compiler did to produce that
> assembly code". Another question, is "how to
> understand how good is the assembler code produced y
> the compiler"
>
> Rgards,
>
> JaaC
>
> --- Mike Rosing <eresrch@eres...> wrote:
> > On Tue, 17 May 2005, Giovanni Parodi wrote:
> >
> > > Thanks a lot for your advice, however I have
> some
> > > problem with the feedback provided by ADI
> > compiler. In
> > > fact for example in CCS there are tools that say
> > you
> > > how much is exploited your pipeline, how are
> > balanced
> > > the acces to the different functional units etc.
> > > I didn-t find nothing like that in ADI, or
> better
> > I
> > > found the pipeline viewer that-s a very
> beautiful
> > > tool, but that cannot be used if you use DMA
> > becuse
> > > the simulator seems not to support this hardware
> > > specific aspect.
> > > Thanks a lot Giovanni
> >
> > the blackfin's pipeline is not so sophisticated as
> > the SHARC's,
> > nor as complicated as some TI parts. I would hope
> > that the
> > tool that helps tell you how well the pipeline is
> > full could
> > also tell the compiler how to optimize things
> > better. At present
> > this is a state of the art challenge.
> >
> > I think the VDSP comes with a profiling tool so
> you
> > can see how many clock
> > cycles you spend in any one location. That may
> help
> > point you to places
> > that need further optimization, but it won't
> > necessarily tell you how full
> > your pipes are.
> >
> > Patience, persistence, truth,
> > Dr. mike > Jaime Andr Aranguren Cardona
> jaime.aranguren@jaim...
> jaime.aranguren@jaim... >
>
> __________________________________
>
>
___________________________________
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