Hi
i am using the ADSP BF533 EZ-KIT LITE REV 1.5
which a BF533 REVISION 0.2
Using PPI whith DMA i got a problem.
I am using PPI RX in GP Mode whith 1 external
Frame sync.
As said in Chapter 11 (PPI) of the Hardware Reference Manual
After setting up the PPI and the DMA, a Transfer will occur when the external
Frame sync occurs.
But 1 Transfer starts direktly after setting up the PPI and DMA, whithout a
assertion of the external Frame sync on PPI_FS1.
why is a DMA transfer startet when setting up the DMA/PPI ?
According to DMA Operation Flow Figure 9-14 and 9-15 from Chapter 9 (DMA)
It is normal that DMA Transfer occurs when DMA is setup, but for the PPI DMA
this is in contrast to what is standing in chapter 11 (PPI)
so is it truly normal that when setup DMA ON PPI 1 Transfer is Startet whithout
looking on PPI_FS1 and so it is only bad documented ?
Or might i am doing somthing wrong which my init ?
my code is here:
void initPPIREAD(void)
{
*pDMA0_START_ADDR = ppiBuffer;
*pDMA0_PERIPHERAL_MAP = 0x0;
*pDMA0_X_COUNT = 64;
*pDMA0_X_MODIFY = 1;
*pDMA0_CONFIG = (WNR | WDSIZE_8 | RESTART | FLOW_1 | DI_EN);
*pDMA0_CONFIG = (*pDMA0_CONFIG | DMAEN);
*pPPI_COUNT = 63;
*pPPI_DELAY = 0;
*pPPI_CONTROL = 0xC00C; // POLS=1 POLC=1 XFR_TYPE
*pPPI_CONTROL = 0xC00D; // PORT_EN
}
void Init_Interrupts(void)
{
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff21;
*pSIC_IAR2 = 0xffff5fff;
register_handler(ik_ivg8, DMA0_PPI_ISR);
register_handler(ik_ivg12, FlagA_ISR);
*pSIC_IMASK = 0x00090300; //ivg8 und ivg9 und ivg12
ssync();
}
in my main i do
Init_Interrupts();
initPPIREAD();
switching the order of the inits i tried
switching order of DMA init and PPI init i tried
all the same problem after init 1 time Read occurs
after that all works like it should ....
any suggestions ?
thanks
dennis noermann
