AW: ADSP-21061 (SHARC) programming issue
Von: Yipeng Tang
Gesendet am: Freitag, 27. Januar 2006 18:10
Betreff: [adsp] ADSP-21061 (SHARC) programming issue
Hi DSP guru,
I am programming for ADSP21061. The code was developed by other developer
who left long time ago. I am trying to understand his code, but I don't
have experience on DSP at all. The DSP is used as a slave that is
listening to the command sent from the master Micro controller. These
interface signals include IRQ0, dsp_data[31:0] SPR0I, etc. According to what I understand, IRQ0 is used to tell DSP to be ready to
receive input data (dsp_data[31:0]). If IRQ0 is 1, then get_command( )
will kick off.
Same as SPR0I. If SPR01 is '1', then isr_handler( ) will kick off.
That is what I understand from the following code. ========================================================================
Main ( )
} get_command(int sig_num)
dsp_command = dm_port.idata;
void isr_handler(int sig_num)
Since get_command ( ) is going to use dm_port data as a command. I assume
the data on dm_port is dsp_data[31:0]. Does that mean dsp_data[31:0]
should be available before IRQ0 becomes '1'? If dsp_data[31:0] come later
then IRQ0, will these data not be latched into DSP?
No, this is not required. dm_port.idata is evaluated in the beginning of
the interrupt service routine. This interrupt service routine is activated
by the processor, but the execution of this routine depends on different
issues: global interrupt enable register - other interrupts actually being
processed, when IRQ0 occurs.
Therefore you cannot be sure that get_command() will be processed
immediately when IRQ0 occurs.
For dm_port.idata this means, that its contents are evaluated at a certain
time later (and you cannot rely on a fixed value for the delay!) According to what the master Micro-controller said, Micro-controller won't
give the dsp_data[31:0] until RD and MS<1> signals from DSP is pulled down.
Where is the DSP code to pull RD, MS<1> or WR up and down?
That depends. Without making assumptions about the signal lines, it's not
easy to tell. There are RD/WR flags which are required to control external
Since memory transfers are usually processed by the internal DMA chip of
the DSP, it will certainly be responsible for the line control.
However, RD and WR might be "self-made" general-purpose lines which have to
be set/cleared by explicit DSP code.
Check the pins on the DSP, to which these signals are connected, find them
in the hardware description/manual of the DSP, then you can find out, what
they really do.
What I guess is, that these lines are used to synchronize bus accesses so
that DSP and micro can write on this bus without conflicts.
And I guess, that there's some additional code describing how the DMA
processor captures data from dsp_data and providing it in a latched memory
In this case, you could possibly rely on the contents being present at the
time of the interrupt's servicing. You'll have to find out...
Is set_flag ( ) system function?
Take it as a system function or library call. In your case, I'd always
check the code behind such a function. This isn't difficult, since you
could just step through this portion of code in the debugger or simulator
and watch in the disassembly window of the IDDE, what happens while
executing this procedure.
Although it seems trivial, it might give you more insight, and help to
avoid errors because you misunderstand anything.
(Be aware, that there are certain circumstances, where the compiler and
linker might be happy with your code, though it wouldn't work, since such a
library call has no code behind - compiling with different optimizer
levels, enabling/disabling certain compiler pragmas / defines differently
in different modules, might do awkward things.
Especially, if you try to revive outaged or unknown code modules, be aware
of every evil thing which is imaginable, and even worse...! )
Bernhard I attached a diagram in this email for your reference.
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