Hi
We have been disappointed with the performance of the VisualDSP++ C++
compiler, for code written in C or C++. Manual coding in assembler
often yields much faster code.
In contrast, the TI DSP C compiler seems to yield excellent, optimised
code.
Do other people share this opinion?
Can anyone at ADI comment on whether this issue is being addressed?
David
VisualDSP++ Compiler Optimisation Performance
Started by ●May 10, 2006
Reply by ●May 15, 20062006-05-15
I
Hi
I want to interface TS 201 to Xilinx Virtex II PRO FPGA through Link port (Bittware T2 PCI Card). Whether any IP Cores are available for this? I have a RF Board with 4-bit ADC. Those ADC O/Ps are in LVTTL or LVCMOS levels (Basically like Discrete I/Os for FPGA). This available data + a Clock from this ADC will be connected to the FPGA and need to be converted to TS201 Link port format. Kindly give me some solution to do this. If IP Cores are not available, give some other ideas to do this. Thank you.
By Aman
---------------------------------
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Hi
I want to interface TS 201 to Xilinx Virtex II PRO FPGA through Link port (Bittware T2 PCI Card). Whether any IP Cores are available for this? I have a RF Board with 4-bit ADC. Those ADC O/Ps are in LVTTL or LVCMOS levels (Basically like Discrete I/Os for FPGA). This available data + a Clock from this ADC will be connected to the FPGA and need to be converted to TS201 Link port format. Kindly give me some solution to do this. If IP Cores are not available, give some other ideas to do this. Thank you.
By Aman
---------------------------------
Talk is cheap. Use Yahoo! Messenger to make PC-to-Phone calls. Great rates starting at 1ยข/min.
Reply by ●May 15, 20062006-05-15
On Sun, 14 May 2006, aman wrote:
> I want to interface TS 201 to Xilinx Virtex II PRO FPGA through Link
>port (Bittware T2 PCI Card). Whether any IP Cores are available for
>this? I have a RF Board with 4-bit ADC. Those ADC O/Ps are in LVTTL
>or LVCMOS levels (Basically like Discrete I/Os for FPGA). This available
>data + a Clock from this ADC will be connected to the FPGA and need to be
>converted to TS201 Link port format. Kindly give me some solution to do
>this. If IP Cores are not available, give some other ideas to do this.
>Thank you.
Howdy Aman,
I'm jelous. That's a fun project. Have you got Xilinx tools for
compiling either VHDL or schematic entry models? I don't know if their
free web tool will do that part, but it's worth a check.
With schematic it's pretty easy to set up the virtual logic that will
collect the bits in the ADC format, and also to create the output boxes
that will spit out Link port format. The translation in the middle is
open to interpretation and that's where the fun is. Think about the
timing and which clock is most important. Double buffered registers or
dual ported ram might come in mighty handy.
With VHDL, lay out the schematic on paper and then convert. Once you have
a model typed in you can mess with it and make more subtle connections,
but it really helps to start with an overall diagram of what you want.
Some tools will create a diagram from the VHDL, but it can be pretty
confusing if you don't start with a good idea of what you want. I don't
think the translation you need is very complicated, but getting the timing
correct will be the fun part :-)
Patience, persistence, truth,
Dr. mike
> I want to interface TS 201 to Xilinx Virtex II PRO FPGA through Link
>port (Bittware T2 PCI Card). Whether any IP Cores are available for
>this? I have a RF Board with 4-bit ADC. Those ADC O/Ps are in LVTTL
>or LVCMOS levels (Basically like Discrete I/Os for FPGA). This available
>data + a Clock from this ADC will be connected to the FPGA and need to be
>converted to TS201 Link port format. Kindly give me some solution to do
>this. If IP Cores are not available, give some other ideas to do this.
>Thank you.
Howdy Aman,
I'm jelous. That's a fun project. Have you got Xilinx tools for
compiling either VHDL or schematic entry models? I don't know if their
free web tool will do that part, but it's worth a check.
With schematic it's pretty easy to set up the virtual logic that will
collect the bits in the ADC format, and also to create the output boxes
that will spit out Link port format. The translation in the middle is
open to interpretation and that's where the fun is. Think about the
timing and which clock is most important. Double buffered registers or
dual ported ram might come in mighty handy.
With VHDL, lay out the schematic on paper and then convert. Once you have
a model typed in you can mess with it and make more subtle connections,
but it really helps to start with an overall diagram of what you want.
Some tools will create a diagram from the VHDL, but it can be pretty
confusing if you don't start with a good idea of what you want. I don't
think the translation you need is very complicated, but getting the timing
correct will be the fun part :-)
Patience, persistence, truth,
Dr. mike
